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公开(公告)号：US20210263098A1
公开(公告)日：2021-08-26
申请号：US16801447
申请日：2020-02-26
Applicant: Silicon Laboratories Inc.
Inventor： Mudit Srivastava , Raghavendra Pai Kateel , HengWee Cheng , Anil Shirwaikar
IPC: G01R31/3177 , G06F21/74 , G01R31/317
Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.
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公开(公告)号：US20210255678A1
公开(公告)日：2021-08-19
申请号：US16791210
申请日：2020-02-14
Applicant: Silicon Laboratories Inc.
Inventor： Rex Tak Ying Wong , Michael R. May , Pio Balmelli
IPC: G06F1/26 , G01R19/165 , G06F13/40
Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.
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公开(公告)号：US20210255653A1
公开(公告)日：2021-08-19
申请号：US16793142
申请日：2020-02-18
Applicant: Silicon Laboratories Inc.
Inventor： RICKY SETIAWAN , HUA BENG CHAN , REX TAK YING WONG
Abstract: In an embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a first loop circuit coupled to the amplifier to receive the comparison signal and output a first feedback voltage for the amplifier to use as the feedback voltage in a first mode of operation; and a second loop circuit coupled to the amplifier. The second loop circuit may be configured to receive the comparison signal and output a second feedback voltage for the amplifier to use as the feedback voltage in a second mode of operation. The second feedback voltage may be greater than the first feedback voltage, and the second loop circuit may output a regulated voltage based on the comparison signal.
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94.发明申请公开(公告)号：US20210215765A1
公开(公告)日：2021-07-15
申请号：US17215723
申请日：2021-03-29
Applicant: Silicon Laboratories Inc.
Inventor： Jeffrey L. Sonntag , Timothy J. Dupuis , Jiwen Xiao
IPC: G01R31/387 , G01R31/3832
Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.
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公开(公告)号：US20210184687A1
公开(公告)日：2021-06-17
申请号：US17186180
申请日：2021-02-26
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
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Patent Agency Ranking
公开(公告)号：US20210176020A1
公开(公告)日：2021-06-10
申请号：US16707401
申请日：2019-12-09
Applicant: Silicon Laboratories Inc.
IPC: H04L1/20 , G01R31/30 , G01R31/317 , G01R29/26
Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.
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公开(公告)号：US11032769B2
公开(公告)日：2021-06-08
申请号：US15845813
申请日：2017-12-18
Applicant: Silicon Laboratories Inc.
Inventor： Partha Sarathy Murali , Nagaraja Reddy Anakala , Ajay Mantha
IPC: H04W52/02 , H04W4/80 , H04W4/029 , H04W4/06 , H04W4/70 , H04W84/18 , H04W84/12 , H04L25/02 , H04L27/06
Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.
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公开(公告)号：US20210157355A1
公开(公告)日：2021-05-27
申请号：US16693559
申请日：2019-11-25
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.
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公开(公告)号：US20210150068A1
公开(公告)日：2021-05-20
申请号：US16687959
申请日：2019-11-19
Applicant: Silicon Laboratories Inc.
Inventor： Javier Elenes
Abstract: Embodiments include cryptographic circuits having isolated operation with respect to embedded sensor operations to mitigate side-channel attacks. A cryptographic circuit, a sensor, and an analog-to-digital converter (ADC) circuit are integrated into an integrated circuit along with a cryptographic circuit. A sensed signal is output with the sensor, and the sensed signal is converted to digital data using the ADC circuit. Further, cryptographic data is generated using one or more secret keys and the cryptographic circuit. The generation of the cryptographic data has isolated operation with respect to the operation of the sensor and the ADC circuit. The isolated operation mitigates side-channel attacks. The isolated operation can be achieved using power supply, clock, and/or reset circuits for the cryptographic circuit that are electrically isolated from similar circuits for the sensor and ADC circuit. The isolated operation can also be achieved using time-division multiplex operations. Other variations can also be implemented.
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公开(公告)号：US20210141661A1
公开(公告)日：2021-05-13
申请号：US16680915
申请日：2019-11-12
Applicant: Silicon Laboratories Inc.
Inventor： Jean-François Deschenes
Abstract: A system and method of minimizing the context saved when the processing unit is disclosed. The kernel attempts to save time and memory by reducing or eliminating the amount of context that is saved or restored in certain situations. Specifically, if there is no currently executing, the kernel does not save any context before switching to another task. Similarly, if there is no new task to execute, the kernel does not restore any context before making the context switch. Rather, the kernel applies a lightweight context. In some embodiments, the idle context uses the ISR stack rather than having a dedicated stack. This system and method reduces the time required for certain context switches and also saves memory.
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