公开(公告)号：US10819354B2

公开(公告)日：2020-10-27

申请号：US16580161

申请日：2019-09-24

Applicant: Silicon Laboratories Inc.

Inventor： Kannanthodath V. Jayakumar ,  James D. Barnette

IPC: H03L7/095 ,  H03L7/093 ,  H03L7/099 ,  H03L7/087

Abstract: A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.

公开(公告)号：US20200162081A1

公开(公告)日：2020-05-21

申请号：US16580161

申请日：2019-09-24

Applicant: Silicon Laboratories Inc.

Inventor： Kannanthodath V. Jayakumar ,  James D. Barnette

IPC: H03L7/095 ,  H03L7/099 ,  H03L7/093

Abstract: A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.

公开(公告)号：US20210176020A1

公开(公告)日：2021-06-10

申请号：US16707401

申请日：2019-12-09

Applicant: Silicon Laboratories Inc.

Inventor： Raghunandan K. Ranganathan ,  Kannanthodath V. Jayakumar ,  Srisai R. Seethamraju

IPC: H04L1/20 ,  G01R31/30 ,  G01R31/317 ,  G01R29/26

Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

公开(公告)号：US10608649B1

公开(公告)日：2020-03-31

申请号：US16194678

申请日：2018-11-19

Applicant: Silicon Laboratories Inc.

Inventor： Kannanthodath V. Jayakumar ,  James David Barnette

IPC: H03L7/087 ,  H03L7/18 ,  H03L7/093 ,  H03L7/089

Abstract: An apparatus for providing a clock signal based on a received clock signal includes a time-to-digital converter configured to generate timestamp information based on the received clock signal. The apparatus includes a first filter configured to generate clock period information based on the timestamp information. The apparatus includes a phase monitor circuit. The phase monitor circuit includes a second filter configured to provide a mean period signal of the received clock signal based on the clock period information. The phase monitor includes a phase error detection circuit configured to generate a phase error indicator based on a threshold difference value and a difference between the clock period information and expected clock period information. The expected clock period information is based on the mean period signal.

公开(公告)号：US11228403B2

公开(公告)日：2022-01-18

申请号：US16707401

申请日：2019-12-09

Applicant: Silicon Laboratories Inc.

Inventor： Raghunandan K. Ranganathan ,  Kannanthodath V. Jayakumar ,  Srisai R. Seethamraju

IPC: H04L1/20 ,  G01R31/30 ,  G01R29/26 ,  G01R31/317

Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

公开(公告)号：US20210159904A1

公开(公告)日：2021-05-27

申请号：US16697613

申请日：2019-11-27

Applicant: Silicon Laboratories Inc.

Inventor： Kannanthodath V. Jayakumar

IPC: H03L7/099 ,  H03L7/07

Abstract: An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.

公开(公告)号：US11018679B1

公开(公告)日：2021-05-25

申请号：US16697613

申请日：2019-11-27

Applicant: Silicon Laboratories Inc.

Inventor： Kannanthodath V. Jayakumar

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/07

Abstract: An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.