An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.