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公开(公告)号：US09813655B2
公开(公告)日：2017-11-07
申请号：US15237103
申请日：2016-08-15
发明人： Serge Hembert
CPC分类号： H04N5/44 , G09G5/006 , G09G2340/02 , G09G2370/20 , G09G2370/22 , H04R2420/05
摘要： A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.
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公开(公告)号：US09698183B2
公开(公告)日：2017-07-04
申请号：US14744482
申请日：2015-06-19
IPC分类号： H04N5/374 , H01L27/146 , H04N5/378 , H04N5/367 , H04N17/00 , H04N5/3745
CPC分类号： H01L27/14612 , H01L27/14643 , H04N5/367 , H04N5/374 , H04N5/3742 , H04N5/3745 , H04N5/378 , H04N17/002
摘要： A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.
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公开(公告)号：US12124815B2
公开(公告)日：2024-10-22
申请号：US17747101
申请日：2022-05-18
摘要： A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.
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公开(公告)号：US20240243712A1
公开(公告)日：2024-07-18
申请号：US18411748
申请日：2024-01-12
发明人： Vratislav MICHAL , Samuel FOULON
CPC分类号： H03F3/45183 , H03F1/3205 , H03F3/45744
摘要： A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.
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公开(公告)号：US20240231410A9
公开(公告)日：2024-07-11
申请号：US18379262
申请日：2023-10-12
发明人： Julien GOULIER , Nicolas GOUX , Marc JOISSON
CPC分类号： G05F3/262 , G05F1/468 , H03K17/18 , H03K17/22 , H03F3/45179
摘要： An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.
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公开(公告)号：US12008244B2
公开(公告)日：2024-06-11
申请号：US17810093
申请日：2022-06-30
发明人： Jawad Benhammadi
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0655 , G06F3/0679
摘要： The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.
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公开(公告)号：US20240171424A1
公开(公告)日：2024-05-23
申请号：US18509618
申请日：2023-11-15
申请人： STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics (Alps) SAS
发明人： Fred Rennig , Giovanni Luca Torrisi , Manuel Gaertner , Philippe Sirito-Olivier , Fritz Burkhardt , Aldo Occhipinti
IPC分类号： H04L12/40
CPC分类号： H04L12/40006 , H04L2012/40215
摘要： A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.
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公开(公告)号：US11988776B2
公开(公告)日：2024-05-21
申请号：US18359477
申请日：2023-07-26
发明人： Romain David , Xavier Branca
CPC分类号： G01S7/484 , G01S17/10 , H01S5/0428 , H01S5/062
摘要： The present disclosure relates to a driver circuit for an optical light emitter of a ranging device, the driver circuit comprising: an inductor having a first of its nodes coupled to a current driver; a first branch comprising a first switch coupled between the second node of the inductor and a first supply voltage rail; a second branch for conducting a current through the optical light emitter, the second branch being coupled between the second node of the inductor and the first supply voltage rail; and a current sensor configured to detect the current passing through the inductor and to provide a feedback signal to the current driver.
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公开(公告)号：US11907156B2
公开(公告)日：2024-02-20
申请号：US17457553
申请日：2021-12-03
发明人： Michael Soulie , Thomas Martin
CPC分类号： G06F15/7807 , G06F1/08 , G06F1/14
摘要： According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.
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公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC分类号： H04L41/0803 , H04L49/109 , G06F21/85
CPC分类号： H04L49/109 , G06F21/85 , H04L41/0803
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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