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公开(公告)号：US12230095B2
公开(公告)日：2025-02-18
申请号：US17993166
申请日：2022-11-23
Applicant: ANGEL GROUP CO., LTD.
Inventor： Yasushi Shigeta
Abstract: According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.
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公开(公告)号：US12164884B2
公开(公告)日：2024-12-10
申请号：US17003334
申请日：2020-08-26
Applicant: Intel Corporation
Inventor： Shuai Mu , Cristina S. Anderson , Subramaniam Maiyuran
Abstract: Examples described herein relate to instructions to request performance of tanh and sigmoid instructions. For example, a compiler can generate native tanh instructions to perform tanh. In some examples, a tanh function can be compiled into instructions that include an instruction to perform either tanh(input) or tanh(input)/input depending on a value of the input to generate an intermediate output; an instruction to cause a performance of generation of scale factor based on the input; and an instruction to cause performance of a multiplication operation on the intermediate result with the scale factor. For example, a sigmoid function can be compiled to cause a math pipeline to perform a range check and performs operations based on a range.
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公开(公告)号：US12112596B2
公开(公告)日：2024-10-08
申请号：US18071004
申请日：2022-11-29
Applicant: ANGEL GROUP CO., LTD.
Inventor： Yasushi Shigeta
CPC classification number: G07F17/322 , A63F1/18 , G06F7/548 , G07F17/3241 , G07F17/3248 , G07F17/3272 , G07F17/3288 , G07F17/3293 , A63F2011/0058
Abstract: According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.
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公开(公告)号：US12086568B2
公开(公告)日：2024-09-10
申请号：US18134737
申请日：2023-04-14
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Rupesh Singh
CPC classification number: G06F7/548 , G06F7/5443 , H03K3/037 , H03K5/01 , H03K2005/00078
Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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公开(公告)号：US12057804B2
公开(公告)日：2024-08-06
申请号：US16960348
申请日：2018-08-28
Applicant: SUNG CHANG CO., LTD
Inventor： Jae Jin Lee
Abstract: A solar module installation method for efficient use of sunlight according to the present invention comprises the steps of: determining a reflection panel inclination angle of a solar reflection panel such that the panel is inclined by a predetermined angle with respect to a virtual horizontal plane; calculating a second projection distance by using a first projection height, a second projection height, and a first projection distance; and determining a panel inclination angle between the solar panel and a second virtual horizontal plane or determining the length of the solar panel so that the other end of the solar panel is positioned at the calculated second projection distance, and installing a solar module according to the determined panel inclination angle or panel length.
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Patent Agency Ranking
公开(公告)号：US11954966B2
公开(公告)日：2024-04-09
申请号：US17843424
申请日：2022-06-17
Applicant: ANGEL GROUP CO., LTD.
Inventor： Yasushi Shigeta
CPC classification number: G07F17/322 , A63F1/18 , G06F7/548 , G07F17/3241 , G07F17/3248 , G07F17/3272 , G07F17/3288 , G07F17/3293 , A63F2011/0058
Abstract: According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.
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公开(公告)号：US11804907B2
公开(公告)日：2023-10-31
申请号：US17376083
申请日：2021-07-14
Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
Inventor： Joshua Beun
CPC classification number: H04B10/60 , G06F7/548 , H04B10/50 , H04L5/0048
Abstract: A finite rate of innovation (FRI) communications system includes a reference signal generator, an FRI modulator configured to apply an FRI kernel and encode information onto the reference signal, and a transmitter configured to transmit the encoded signal. The FRI kernel is one of a sinc function kernel or a Gaussian kernel. A receiver unit is configured to receive an encoded signal, convert the encoded signal into a digital signal, and demodulate and recover information from finite rate of innovation parameters in the digital signal.
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公开(公告)号：US20220319267A1
公开(公告)日：2022-10-06
申请号：US17843424
申请日：2022-06-17
Applicant: ANGEL GROUP CO., LTD.
Inventor： Yasushi SHIGETA
Abstract: According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.
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公开(公告)号：US20220035630A1
公开(公告)日：2022-02-03
申请号：US17346891
申请日：2021-06-14
Applicant: Intel Corporation
Inventor： Venkateswara R. MADDURI , Elmoustapha OULD-AHMED-VALL , Robert VALENTINE , Jesus CORBAL , Mark J. CHARNEY , Carl MURRAY , Milind GIRKAR , Bret TOLL
Abstract: Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.
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公开(公告)号：US20210342120A1
公开(公告)日：2021-11-04
申请号：US17378916
申请日：2021-07-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prasanth Viswanathan Pillai , Richard Mark Poley , Venkatesh Natarajan , Alexander Tessarolo
IPC: G06F7/548
Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
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