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1.发明授权公开(公告)号：US11463098B2
公开(公告)日：2022-10-04
申请号：US17342416
申请日：2021-06-08
发明人： Ankur Bal , Sri Ram Gupta , Rupesh Singh
摘要： An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.
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公开(公告)号：US11094354B2
公开(公告)日：2021-08-17
申请号：US17015271
申请日：2020-09-09
发明人： Ankur Bal , Rupesh Singh , Vivek Tripathi
摘要： A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
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公开(公告)号：US12093193B2
公开(公告)日：2024-09-17
申请号：US17067967
申请日：2020-10-12
发明人： Ankur Bal , Rupesh Singh
CPC分类号： G06F13/1668 , G06F7/4876 , G06F9/3001 , G06F9/30021 , G06F17/16
摘要： Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.
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公开(公告)号：US11989148B2
公开(公告)日：2024-05-21
申请号：US17548101
申请日：2021-12-10
发明人： Ankur Bal , Rupesh Singh
摘要： An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.
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公开(公告)号：US11092993B2
公开(公告)日：2021-08-17
申请号：US16437705
申请日：2019-06-11
发明人： Ankur Bal , Rupesh Singh
摘要： A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.
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公开(公告)号：US12086568B2
公开(公告)日：2024-09-10
申请号：US18134737
申请日：2023-04-14
发明人： Ankur Bal , Rupesh Singh
CPC分类号： G06F7/548 , G06F7/5443 , H03K3/037 , H03K5/01 , H03K2005/00078
摘要： A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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公开(公告)号：US20190190688A1
公开(公告)日：2019-06-20
申请号：US15846560
申请日：2017-12-19
发明人： Rupesh Singh , Ankur Bal
IPC分类号： H04L7/00
摘要： Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
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公开(公告)号：US10218380B1
公开(公告)日：2019-02-26
申请号：US16036004
申请日：2018-07-16
发明人： Ankur Bal , Rupesh Singh
摘要： Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.
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公开(公告)号：US11656848B2
公开(公告)日：2023-05-23
申请号：US16988912
申请日：2020-08-10
发明人： Ankur Bal , Rupesh Singh
CPC分类号： G06F7/548 , G06F7/5443 , H03K3/037 , H03K5/01 , H03K2005/00078
摘要： A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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公开(公告)号：US11417371B2
公开(公告)日：2022-08-16
申请号：US17374304
申请日：2021-07-13
发明人： Ankur Bal , Rupesh Singh , Vivek Tripathi
摘要： A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
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