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公开(公告)号：US20220214880A1
公开(公告)日：2022-07-07
申请号：US17143989
申请日：2021-01-07
摘要： A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.
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2.发明授权公开(公告)号：US09311274B2
公开(公告)日：2016-04-12
申请号：US14056111
申请日：2013-10-17
CPC分类号： G06F17/142
摘要： A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2N)×(10×log2N) times.
摘要翻译： 系统包括存储体和控制单元。 控制单元被配置为通过对N个输入项执行FFT计算，并且通过对（1/2×log2N）×（10×log2N）倍的存储体进行基于合并的二进制蝶形运算进行FFT计算。
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公开(公告)号：US11733969B2
公开(公告)日：2023-08-22
申请号：US17378916
申请日：2021-07-19
IPC分类号： G06F7/548
CPC分类号： G06F7/548
摘要： In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
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公开(公告)号：US11099815B2
公开(公告)日：2021-08-24
申请号：US16934539
申请日：2020-07-21
IPC分类号： G06F7/548
摘要： In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
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公开(公告)号：US20190369962A1
公开(公告)日：2019-12-05
申请号：US16000736
申请日：2018-06-05
IPC分类号： G06F7/548
摘要： In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
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公开(公告)号：US20190286418A1
公开(公告)日：2019-09-19
申请号：US16432257
申请日：2019-06-05
IPC分类号： G06F7/535
摘要： A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.
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公开(公告)号：US20170033955A1
公开(公告)日：2017-02-02
申请号：US15083549
申请日：2016-03-29
CPC分类号： H04L25/49 , G06F13/4282 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0083 , H04L1/009 , H04L1/0091 , H04L5/0044 , H04L25/0266
摘要： Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a digital clock signal; a clock signal controller to enable the clock signal generator; a line break signal generator to, in response to an expiration of a time period, trigger the transmission of a transmission line check frame; a data integrity check generator to generate error detection data corresponding to first data to be transmitted via the transmission port; a signal framer to: generate a first data frame having a preamble, second data, third data, the first data, the error detection data, and fourth data; and generate the transmission line check frame.
摘要翻译： 公开了执行串行通信的方法和装置。 示例串行数据发送器包括：时钟信号发生器，用于产生数字时钟信号; 时钟信号控制器，用于使能时钟信号发生器; 断线信号发生器响应于时间段的到期触发传输线路检查帧的传输; 数据完整性检查生成器，用于生成与通过传输端口发送的第一数据相对应的错误检测数据; 信号成帧器，用于：产生具有前导码，第二数据，第三数据，第一数据，错误检测数据和第四数据的第一数据帧; 并生成传输线检查帧。
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公开(公告)号：US20140129908A1
公开(公告)日：2014-05-08
申请号：US13669447
申请日：2012-11-06
IPC分类号： H03M13/23
CPC分类号： H03M13/4107
摘要： A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.
摘要翻译： 适用于维特比解码的解码系统包括包括状态度量阵列，蝶形单元和约束长度多路复用器的解码器。 状态度量阵列包括寄存器，其中每个寄存器被布置成存储用于处理的状态度量。 蝶形单元包括一组蝴蝶元件，其中每个蝶形元件被布置成与蝴蝶单元中的其它蝶形元件并行生成中间状态度量。 约束长度多路复用器单元被布置为响应于中间状态度量和存储在约束长度寄存器中的维特比约束长度值来生成新的状态度量。 也可以响应于约束长度来生成转换位。
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公开(公告)号：US12032966B2
公开(公告)日：2024-07-09
申请号：US17958219
申请日：2022-09-30
CPC分类号： G06F9/3869 , G06F7/02
摘要： A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.
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公开(公告)号：US20210342120A1
公开(公告)日：2021-11-04
申请号：US17378916
申请日：2021-07-19
IPC分类号： G06F7/548
摘要： In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
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