公开(公告)号：US20210057335A1

公开(公告)日：2021-02-25

申请号：US16547847

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Guanyu Luo ,  Chin-Lung Chung ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a graphene layer between the second contact feature and the first contact feature.

公开(公告)号：US20200312708A1

公开(公告)日：2020-10-01

申请号：US16712430

申请日：2019-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/535

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

公开(公告)号：US10763211B2

公开(公告)日：2020-09-01

申请号：US16048921

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

公开(公告)号：US20200098685A1

公开(公告)日：2020-03-26

申请号：US16534411

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/027

Abstract: A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

公开(公告)号：US10510657B2

公开(公告)日：2019-12-17

申请号：US15715327

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522

Abstract: A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.

公开(公告)号：US09721894B2

公开(公告)日：2017-08-01

申请号：US15361699

申请日：2016-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang Fu ,  Hsien-Chang Wu ,  Li-Lin Su ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US09219033B2

公开(公告)日：2015-12-22

申请号：US14221509

申请日：2014-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/00 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract translation: 本公开内容涉及使用预填充工艺形成以减少空隙的金属互连层，以及相关联的方法。 在一些实施例中，金属互连层具有设置在衬底上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。

公开(公告)号：US20150270215A1

公开(公告)日：2015-09-24

申请号：US14221509

申请日：2014-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/288 ,  H01L21/768 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract translation: 本公开内容涉及使用预填充工艺形成以减少空隙的金属互连层，以及相关联的方法。 在一些实施例中，金属互连层具有设置在衬底上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。

公开(公告)号：US12218060B2

公开(公告)日：2025-02-04

申请号：US17308361

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Meng-Pei Lu ,  Chin-Lung Chung ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

公开(公告)号：US20240258166A1

公开(公告)日：2024-08-01

申请号：US18608673

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.