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公开(公告)号：US12165925B2
公开(公告)日：2024-12-10
申请号：US18354670
申请日：2023-07-19
Inventor： Sai-Hooi Yeong , Kai-Hsuan Lee , Yu-Ming Lin , Chi-On Chui
IPC: H01L21/8234 , H01L21/308 , H01L21/762 , H01L21/764 , H01L21/768 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.
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公开(公告)号：US20240389347A1
公开(公告)日：2024-11-21
申请号：US18789156
申请日：2024-07-30
Inventor： Chia-Ta Yu , Chia-En Huang , Yi-Ching Liu , Yih Wang , Sai-Hooi Yeong , Yu-Ming Lin
Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.
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公开(公告)号：US20240389345A1
公开(公告)日：2024-11-21
申请号：US18785892
申请日：2024-07-26
Inventor： Bo-Feng Young , Chung-Te Lin , Sai-Hooi Yeong , Yu-Ming Lin , Sheng-Chih Lai , Chih-Yu Chang , Han-Jong Chia
Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.
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公开(公告)号：US20240389332A1
公开(公告)日：2024-11-21
申请号：US18780425
申请日：2024-07-22
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC: H10B51/20 , G11C5/06 , G11C11/22 , H01L23/522
Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
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公开(公告)号：US12150311B2
公开(公告)日：2024-11-19
申请号：US18364616
申请日：2023-08-03
Inventor： Bo-Feng Young , Chung-Te Lin , Sai-Hooi Yeong , Yu-Ming Lin , Sheng-Chih Lai , Chih-Yu Chang , Han-Jong Chia
Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.
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Patent Agency Ranking
公开(公告)号：US12150308B2
公开(公告)日：2024-11-19
申请号：US17160378
申请日：2021-01-28
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Yu-Ming Lin , Chih-Yu Chang , Han-Jong Chia
IPC: H01L27/06 , H01L23/522 , H10B12/00 , H10B51/30 , H10B53/40
Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.
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公开(公告)号：US12137569B2
公开(公告)日：2024-11-05
申请号：US18162642
申请日：2023-01-31
Inventor： Chao-I Wu , Yu-Ming Lin , Shih-Lien Linus Lu , Sai-Hooi Yeong , Bo-Feng Young
Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.
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公开(公告)号：US12133390B2
公开(公告)日：2024-10-29
申请号：US18170557
申请日：2023-02-17
Inventor： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong
CPC classification number: H10B51/20 , H01L29/40111 , H01L29/517 , H01L29/518 , H10B41/23 , H10B51/00 , H10B51/10 , H10B51/30
Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.
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公开(公告)号：US20240347489A1
公开(公告)日：2024-10-17
申请号：US18751336
申请日：2024-06-23
Inventor： Meng-Han Lin , Sai-Hooi Yeong , Yu-Ming Lin
IPC: H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1441
Abstract: A device includes stacking structures, first conductive contacts, first drivers and second conductive contacts. Each of the stacking structures includes alternately stacked first conductive lines and first dielectric layers, and the stacking structures are shaped into first staircase structures and second staircase structures at first and second sides, respectively. The first conductive contacts are bonded to the first conductive lines respectively. The second conductive contacts are bonded to the first drivers respectively, wherein the first conductive contacts and the second conductive contacts are bonded and disposed between the first conductive lines and the first drivers.
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公开(公告)号：US12119389B2
公开(公告)日：2024-10-15
申请号：US18360854
申请日：2023-07-28
Inventor： Chun Hsiung Tsai , Kuo-Feng Yu , Yu-Ming Lin , Clement Hsingjen Wann
IPC: H01L29/66 , H01L21/02 , H01L21/265 , H01L29/08 , H01L21/266 , H01L21/3105 , H01L21/762
CPC classification number: H01L29/66545 , H01L21/02164 , H01L21/02332 , H01L21/26513 , H01L29/0847 , H01L29/66553 , H01L29/6659 , H01L29/66795 , H01L21/266 , H01L21/31053 , H01L21/76224 , H01L29/665
Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.
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