公开(公告)号：US10475889B1

公开(公告)日：2019-11-12

申请号：US15997991

申请日：2018-06-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L29/20 ,  H01L29/66 ,  H03F3/21 ,  H01L29/08 ,  H01L29/78

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a semiconductor region disposed adjacent to the substrate, first fin(s) disposed adjacent to the semiconductor region, first gate region(s) disposed adjacent to the first fin(s), first drain contact(s) disposed above the first fin(s), first source contact(s) disposed below the substrate, a second fin disposed above the semiconductor region, and a second gate region, second source contact and second drain contact disposed adjacent to the second fin and above the semiconductor region. First path(s) are formed between the first drain contact(s) and the first source contact(s) for current flow(s) through the first fin(s) in a vertical direction along the first path(s). A second path is formed between the second source contact and the second drain contact for current flow through the second fin in a horizontal direction along the second path.

公开(公告)号：US10461164B2

公开(公告)日：2019-10-29

申请号：US15685877

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H01L29/423 ,  H01L29/66

Abstract: A compound semiconductor field effect transistor (FET) may include gallium nitride (GaN) and alloy material layers. The compound semiconductor FET may also include a pair of L-shaped contacts on the GaN and alloy material layers. The compound semiconductor FET may also include a pair of gate spacers between the L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the L-shaped contacts. The compound semiconductor FET may further include a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts are self-aligned with the base gate.

公开(公告)号：US10453774B1

公开(公告)日：2019-10-22

申请号：US16051528

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Bin Yang ,  Xia Li

IPC: H01L23/373 ,  H01L23/00 ,  H01L27/01 ,  H01L23/66 ,  H01L23/522

Abstract: Aspects generally relate to an integrated circuit including a glass substrate. On a surface of the glass substrate a thermally conductive insulating layer is formed. At least one metal layer is formed above the thermally conductive insulating layer, and a plurality of thermal bumps extend through the at least one metal layer and couple to the thermally conductive insulating layer to dissipate heat from the substrate.

公开(公告)号：US20190181137A1

公开(公告)日：2019-06-13

申请号：US15835810

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Lixin Ge

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/088 ,  H03K19/0185 ,  G06F17/50 ,  H01L21/762

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

公开(公告)号：US10247617B2

公开(公告)日：2019-04-02

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  G01K7/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L49/02 ,  G01K7/18 ,  H01L23/34 ,  H01L23/522 ,  H01L27/06

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US10224368B2

公开(公告)日：2019-03-05

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: G11C11/00 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10186514B1

公开(公告)日：2019-01-22

申请号：US15696630

申请日：2017-09-06

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Xia Li ,  Bin Yang

IPC: H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/205 ,  H01L29/737 ,  H01L21/02 ,  H01L29/66 ,  H01L27/06 ,  G11C11/419 ,  H01L29/20 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate, first well layer formed over substrate from a III-V compound doped with a first type material, and second well layer formed over first well layer from a III-V compound doped with a second type material. Channel layer is formed over second well layer from a III-V compound doped with the first type material. Source and drain regions are formed over channel layer from a III-V compound doped with the first type material, and gate region is formed over channel layer. Bipolar junction transistors (BJTs) are formed such that a data value can be stored in second well layer. Collector tap electrode is configured to provide access to collector of each BJT for reading or writing data.

公开(公告)号：US20190006415A1

公开(公告)日：2019-01-03

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10170610B1

公开(公告)日：2019-01-01

申请号：US15922951

申请日：2018-03-16

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/66

Abstract: In certain aspects, a pseudomorphic high electron mobility transistor (pHEMT) comprises a substrate layer, a bottom barrier layer on the substrate layer, a channel layer on the bottom barrier layer, an upper barrier on the channel layer, and a source and a drain on the upper barrier layer. The source and the drain each has a cap layer, an Ohmic contact layer on the cap layer, and a metal contact layer on the Ohmic contact layer. The Ohmic contact layer has a smaller bandgap than the cap layer. The pHEMT further comprises a gate metal stack on the upper barrier layer.

公开(公告)号：US10062683B1

公开(公告)日：2018-08-28

申请号：US15587837

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L29/15 ,  H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H01L29/737 ,  H01L29/20 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8252 ,  H01L21/768 ,  H01L23/66

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuitry may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.