公开(公告)号：US09299799B2

公开(公告)日：2016-03-29

申请号：US14300835

申请日：2014-06-10

Applicant: International Business Machines Corporation

Inventor： Catherine A. Dubourdieu ,  Martin M. Frank ,  Vijay Narayanan

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28088 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684

Abstract: Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.

Abstract translation: 提供了诸如铁电晶体管和浮栅晶体管的半导体器件，其包括在半导体衬底的表面上形成的外延钙钛矿/掺杂钛酸锶结构。 外延钙钛矿/掺杂的钛酸锶结构包括以任何顺序的掺杂的钛酸锶和钙钛矿型氧化物的叠层。

公开(公告)号：US20150270340A1

公开(公告)日：2015-09-24

申请号：US14221349

申请日：2014-03-21

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/12 ,  H01L21/311 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/78696

Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.

Abstract translation: 在第一半导体材料部分和第二半导体材料部分的交替堆叠上形成一次性栅极结构。 第二半导体材料部分被选择性地移除到第一半导体材料部分以形成悬浮的半导体纳米线。 隔离栅极结构通过第一栅极介电层和第一栅极导体层的沉积和凹陷形成在一次性栅极结构下面的区域中。 在形成栅极间隔物之后，通过选择性沉积半导体材料，在源极区和漏极区上形成源极区和漏极区。 一次性栅极结构通过第二栅极介电层和第二栅极导体层的沉积和图案化而被置换栅极结构代替。 通过一次性栅极结构和隔离的栅极结构来防止悬浮的半导体纳米线的失真。

公开(公告)号：US20150243662A1

公开(公告)日：2015-08-27

申请号：US14699264

申请日：2015-04-29

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

Abstract translation: 半导体结构具有半导体衬底和设置在衬底上的nFET和pFET。 pFET具有形成在半导体衬底的表面上或其表面上的半导体SiGe沟道区，以及覆盖沟道区的氧化物层和覆盖氧化物层的高k电介质层的栅极电介质。 栅电极覆盖在栅极电介质上，并且具有邻接高k层的下金属层，邻接下金属层的清除金属层和与清除金属层邻接的上金属层。 金属层清除了衬底（nFET）中的氧和与氧化物层的SiGe（pFET）界面，导致pFET的Tinv和Vt有效降低，同时缩放Tinv并维持nFET的Vt，导致Vt pFET变得更接近具有缩放Tinv值的类似构造的nFET的Vt。

公开(公告)号：US09034749B2

公开(公告)日：2015-05-19

申请号：US14024733

申请日：2013-09-12

Applicant: International Business Machines Corporation

Inventor： Nicolas L. Breil ,  Cyril Cabral, Jr. ,  Martin M. Frank ,  Claude Ortolland

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28088 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.

公开(公告)号：US08928064B2

公开(公告)日：2015-01-06

申请号：US14030520

申请日：2013-09-18

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/511 ,  H01L21/28044 ,  H01L21/2807 ,  H01L29/42364 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/78

Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

Abstract translation: 一种形成半导体器件的栅极结构的方法，包括在半导体衬底上形成非化学计量的高k栅极电介质层，其中含有界面层的氧化物可以存在于非化学计量的高k栅极电介质层和 半导体衬底。 可以在非化学计量的高k栅极电介质层上形成至少一个栅极导体层。 所述至少一个栅极导体层包括硼半导体合金层。 应用退火工艺，其中在退火工艺期间，非化学计量的高k栅极电介质层从含氧化物界面层去除氧化物材料。 通过在退火过程中除去氧化物材料，使含氧化物的界面层变薄。

公开(公告)号：US08927409B2

公开(公告)日：2015-01-06

申请号：US14046218

申请日：2013-10-04

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/326 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/49

CPC classification number: H01L21/28247 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/326 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.

Abstract translation: 一种设备包括晶片退火工具和耦合到晶片退火工具的多个电极，其中电极被配置为与晶片物理接触，使得当晶片退火时，负电偏压跨越一个或 更多的晶片堆叠。

公开(公告)号：US20140308821A1

公开(公告)日：2014-10-16

申请号：US13863580

申请日：2013-04-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Min Dai ,  Martin M. Frank ,  David F. Hilscher ,  Rishikesh Krishnan ,  Barry P. Linder ,  Claude Ortolland ,  Joseph F. Shepard, JR.

IPC: H01L21/02

CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  C23C16/45525 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/28194 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Abstract translation: 用碱性溶液处理含半导体的电介质材料/氧氮化物/氮化物的表面，以提供表面的羟基终止。 随后通过原子层沉积沉积介电金属氧化物。 羟基终止提供了促进介电金属氧化物的成核和沉积的均匀的表面条件，并且减少了氧化物和介电金属氧化物之间的界面缺陷。 此外，用碱性溶液处理从锗锗合金的表面除去更多的锗原子浓度的锗，从而减少氧化物和电介质金属氧化物的组合的总厚度与不同锗的表面的差异 浓度

公开(公告)号：US20140252492A1

公开(公告)日：2014-09-11

申请号：US13793290

申请日：2013-03-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.

Abstract translation: 一种形成半导体器件的方法，包括在半导体衬底上形成高k栅介质层，其中含有界面层的氧化物可以存在于高k栅介质层和半导体衬底之间。 清除金属堆叠可以形成在高k栅极电介质层上。 可以将清除金属堆叠的清除金属堆叠中的退火工艺应用于其中，其中清除金属堆叠从含氧化物的界面层去除氧化物材料，其中通过除去氧化物材料使含有氧化物的界面层变薄。 栅极导体层形成在高k栅介质层上。 然后对栅极导体层和高k栅极电介质层进行构图以提供栅极结构。 然后在栅极结构的相对侧上形成源极区域和漏极区域。

公开(公告)号：US20140162447A1

公开(公告)日：2014-06-12

申请号：US13709250

申请日：2012-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Lisa F. Edge ,  Martin M. Frank ,  Balasubramanian S. Haran ,  Atsuro Inada ,  Sivananda K. Kanakasabapathy ,  Andreas Knorr ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Soon-cheon Seo

IPC: H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/41791

Abstract: A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括对衬底上的翅片进行图案化，在栅极堆叠的一部分上构图栅极堆叠，以及布置在衬底上的绝缘体层的一部分，在栅极叠层上形成保护屏障， 所述翅片和所述绝缘体层的一部分，所述保护屏障包围所述栅极堆叠，在所述鳍片和所述保护屏障的部分上沉积第二绝缘体层，执行第一蚀刻工艺以选择性地去除所述第二绝缘体层的部分以限定空腔 其暴露鳍片的源极和漏极区域的部分，而不明显地去除保护屏障，以及在空腔中沉积导电材料。

公开(公告)号：US20130309782A1

公开(公告)日：2013-11-21

申请号：US13949512

申请日：2013-07-24

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Catherine A. Dubourdieu ,  Martin M. Frank ,  Bipin Rajendran ,  Alejandro G. Schrott

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0095 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD).

Abstract translation: 所公开的示例性实施例是用于制造相变存储单元的方法。 该方法包括形成底部电极，在底部电极上方的绝缘层中产生孔，在孔中沉积压电材料，在相邻的压电材料附近的孔中沉积相变材料，以及在相变材料上形成顶部电极。 将压电材料沉积在孔中可以包括将压电材料配合到限定孔的至少一个壁，使得压电材料沉积在相变材料和壁之间。 共形沉积可以通过化学气相沉积（CVD）或原子层沉积（ALD）来实现。