公开(公告)号：US20180373633A1

公开(公告)日：2018-12-27

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US20180349288A1

公开(公告)日：2018-12-06

申请号：US15608145

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Eric A. Gouldey ,  Camron B. Rust ,  Brett Ireland ,  Rajesh M. Sankaran

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F11/07

CPC classification number: G06F12/1027 ,  G06F11/07 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/305 ,  G06F2212/6028

Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.

公开(公告)号：US10126985B2

公开(公告)日：2018-11-13

申请号：US14748971

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0888 ,  G06F9/50 ,  G06F12/08 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/0866

Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

公开(公告)号：US20180276394A1

公开(公告)日：2018-09-27

申请号：US15470270

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Mohan K. Nair ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya ,  Zhenfu Chai ,  David M. Lee ,  Pratik M. Marolia

IPC: G06F21/60 ,  H04L29/08 ,  G06F9/44 ,  G06F12/0811

CPC classification number: G06F21/602 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4408 ,  G06F12/0815 ,  G06F13/4282 ,  G06F21/575 ,  G06F21/85 ,  G06F2212/1052 ,  G06F2213/0026 ,  H04L63/04

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

公开(公告)号：US10037288B2

公开(公告)日：2018-07-31

申请号：US15088836

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Francesc Bernat Guim ,  David A. Koufaty ,  Andrea Pellegrini ,  Rajesh M. Sankaran

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1009 ,  G06F21/62 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F12/1081 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.

公开(公告)号：US20180011651A1

公开(公告)日：2018-01-11

申请号：US15207218

申请日：2016-07-11

Applicant: INTEL CORPORATION

Inventor： Rajesh M. Sankaran ,  Prashant Sethi ,  Asit K. Mallick ,  David Woodhouse ,  Rupin H. Vakharwala

IPC: G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/064 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/651 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/683

Abstract: An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.

公开(公告)号：US20170357584A1

公开(公告)日：2017-12-14

申请号：US15688209

申请日：2017-08-28

Applicant: Intel Corporation

Inventor： Sanjay K. KUMAR ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC: G06F12/0804 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

公开(公告)号：US09715453B2

公开(公告)日：2017-07-25

申请号：US14567662

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Dheeraj R. Subbareddy ,  Andrew V. Anderson

IPC: G06F3/06 ,  G06F12/0842 ,  G06F12/02 ,  G06F12/0897 ,  G06F12/1009

CPC classification number: G06F12/0842 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/225 ,  G06F2212/601 ,  G06F2212/7201

Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

公开(公告)号：US09477409B2

公开(公告)日：2016-10-25

申请号：US14318573

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajesh M. Sankaran ,  Murugasamy K. Nachimuthu ,  Richard P. Mangold

IPC: G06F3/06 ,  G11C7/20

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0679 ,  G06F8/71 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4416 ,  G06F11/1417 ,  G06F11/3476 ,  G11C7/20

Abstract: Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了基于非易失性存储器（NVM）技术来加速引导时间归零的存储器的方法和装置。 在一个实施例中，存储设备存储对应于非易失性存储器的一部分的引导版本号。 存储器控制器逻辑导致响应于每个后续引导事件的存储的引导版本号的更新。 存储器控制器逻辑响应于针对非易失性存储器的部分的读操作和存储的引导版本号与当前引导版本号之间的不匹配而返回零。 还公开并要求保护其他实施例。

公开(公告)号：US09372807B2

公开(公告)日：2016-06-21

申请号：US14867027

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/02 ,  G06F9/455 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.