公开(公告)号：US10817447B2

公开(公告)日：2020-10-27

申请号：US15350998

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Camron B. Rust

IPC: G06F13/28 ,  G06F12/1027 ,  G06F12/1081 ,  G06F9/4401

Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.

公开(公告)号：US10248574B2

公开(公告)日：2019-04-02

申请号：US15608145

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Eric A. Gouldey ,  Camron B. Rust ,  Brett Ireland ,  Rajesh M. Sankaran

IPC: G06F12/1081 ,  G06F12/1027 ,  G06F12/0862 ,  G06F11/07 ,  G06F13/16

Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.

公开(公告)号：US20180349288A1

公开(公告)日：2018-12-06

申请号：US15608145

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Eric A. Gouldey ,  Camron B. Rust ,  Brett Ireland ,  Rajesh M. Sankaran

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F11/07

CPC classification number: G06F12/1027 ,  G06F11/07 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/305 ,  G06F2212/6028

Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.

公开(公告)号：US20180137069A1

公开(公告)日：2018-05-17

申请号：US15350998

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Camron B. Rust

IPC: G06F13/28 ,  G06F9/44

CPC classification number: G06F13/28 ,  G06F9/4401 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2212/1041 ,  G06F2212/15 ,  G06F2212/502 ,  G06F2212/651

Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.