公开(公告)号：US20240028381A1

公开(公告)日：2024-01-25

申请号：US18477200

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Shaopeng He ,  Yadong Li ,  Anjali Singhai Jain ,  Eliel Louzoun ,  Israel Ben-Shahar ,  Brad A. Burres ,  Bartosz Pawlowski ,  Anton Nadezhdin ,  Rashmi Hanagal Nagabhushana ,  Rupin H. Vakharwala

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45595 ,  G06F2009/45579

Abstract: A network interface device executes an input/output (I/O) virtualization manager to identify a virtual device defined to include resources of a particular virtual functions in a plurality of virtual functions associated with a physical function of a device. An operation is identified to be performed between the virtual device and a system image hosted by a host system coupled to the network interface device. The network interface device emulates the virtual device in the operation using the I/O virtualization manager.

公开(公告)号：US20190220413A1

公开(公告)日：2019-07-18

申请号：US16361512

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Paula Petrica

IPC: G06F12/0862 ,  G06F12/1036 ,  G06F13/42

CPC classification number: G06F12/0862 ,  G06F12/1036 ,  G06F13/42 ,  G06F2213/0026

Abstract: Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.

公开(公告)号：US10048881B2

公开(公告)日：2018-08-14

申请号：US15207218

申请日：2016-07-11

Applicant: INTEL CORPORATION

Inventor： Rajesh M. Sankaran ,  Prashant Sethi ,  Asit K. Mallick ,  David Woodhouse ,  Rupin H. Vakharwala

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/14

Abstract: An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.

公开(公告)号：US11513979B2

公开(公告)日：2022-11-29

申请号：US17187271

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20210209037A1

公开(公告)日：2021-07-08

申请号：US17187271

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20210149815A1

公开(公告)日：2021-05-20

申请号：US17129496

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Saurabh Gayen ,  Philip R. Lantz ,  Dhananjay A. Joshi ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Narayan Ranganathan ,  Sanjay Kumar

IPC: G06F12/10 ,  G06F12/0875 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Techniques for offload device address translation fetching are disclosed. In the illustrative embodiment, a processor of a compute device sends a translation fetch descriptor to an offload device before sending a corresponding work descriptor to the offload device. The offload device can request translations for virtual memory address and cache the corresponding physical addresses for later use. While the offload device is fetching virtual address translations, the compute device can perform other tasks before sending the corresponding work descriptor, including operations that modify the contents of the memory addresses whose translation are being cached. Even if the offload device does not cache the translations, the fetching can warm up the cache in a translation lookaside buffer. Such an approach can reduce the latency overhead that the offload device may otherwise incur in sending memory address translation requests that would be required to execute the work descriptor.

公开(公告)号：US20190102326A1

公开(公告)日：2019-04-04

申请号：US15721777

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/1009

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

公开(公告)号：US10248574B2

公开(公告)日：2019-04-02

申请号：US15608145

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Eric A. Gouldey ,  Camron B. Rust ,  Brett Ireland ,  Rajesh M. Sankaran

IPC: G06F12/1081 ,  G06F12/1027 ,  G06F12/0862 ,  G06F11/07 ,  G06F13/16

Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.

公开(公告)号：US12210660B2

公开(公告)日：2025-01-28

申请号：US17548170

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Anna Trikalinou ,  Abhishek Basak ,  Rupin H. Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F21/83 ,  G06F21/62 ,  G06F21/78

Abstract: In one embodiment, a read request is received from a peripheral device across an interconnect, with the read request including a process identifier and an encrypted virtual address. One or more keys are obtained based on the process identifier of the read request, and the encrypted virtual address of the read request is decrypted based on the one or more keys to obtain an unencrypted virtual address. Encrypted data is retrieved from memory based on the unencrypted virtual address, and the encrypted data is decrypted based on the one or more keys to obtain plaintext data. The plaintext data is transmitted to the peripheral device across the interconnect.

公开(公告)号：US20230013023A1

公开(公告)日：2023-01-19

申请号：US17951024

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Philip R. Lantz

IPC: G06F12/1081 ,  G06F12/0891

Abstract: In one embodiment, an apparatus includes a processor comprising an address translation cache (ATC); a shared work queue (SWQ) associated with the ATC, and a port to couple to a host processor over a Peripheral Component Interconnect Express (PCIe)-based link. The apparatus also includes circuitry to receive address translation information from a memory management unit of the host processor that includes virtual memory address to physical memory address translations, store the address translation information in the ATC, receive an invalidation command from the host processor indicating an invalidation of address translation information stored in the ATC, modify the address translation information in the ATC based on the invalidation command, and store completion data in a memory location indicated by the invalidation command.