Invention Grant
- Patent Title: Restricted address translation to protect against device-TLB vulnerabilities
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Application No.: US15207218Application Date: 2016-07-11
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Publication No.: US10048881B2Publication Date: 2018-08-14
- Inventor: Rajesh M. Sankaran , Prashant Sethi , Asit K. Mallick , David Woodhouse , Rupin H. Vakharwala
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/1009 ; G06F12/1081 ; G06F12/14

Abstract:
An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.
Public/Granted literature
- US20180011651A1 RESTRICTED ADDRESS TRANSLATION TO PROTECT AGAINST DEVICE-TLB VULNERABILITIES Public/Granted day:2018-01-11
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