公开(公告)号：US12135581B2

公开(公告)日：2024-11-05

申请号：US17955234

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Debendra Das Sharma ,  Daniel S. Froelich ,  Sean O. Stalley

IPC: G06F1/14 ,  G06F13/42 ,  H04B1/7073 ,  H04L69/14

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

公开(公告)号：US20230022948A1

公开(公告)日：2023-01-26

申请号：US17955234

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Debendra Das Sharma ,  Daniel S. Froelich ,  Sean O. Stalley

IPC: G06F1/14 ,  G06F13/42 ,  H04B1/7073

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

公开(公告)号：US20170063508A1

公开(公告)日：2017-03-02

申请号：US14843883

申请日：2015-09-02

Applicant: Intel Corporation

Inventor： Sean O. Stalley

IPC: H04L5/00 ,  H04L12/26 ,  H04B1/02

CPC classification number: H04L47/39 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0656 ,  H04B1/02 ,  H04L5/0055 ,  H04L43/08 ,  H04L43/0864 ,  H04L43/0888 ,  H04L47/10 ,  H04L47/12 ,  H04L47/28 ,  H04L47/30 ,  H04L47/365 ,  H04W28/02

Abstract: Described is an apparatus which comprises: a transmitter; an input-output (I/O) interface coupled to the transmitter; and logic to split data for transmission into a plurality of packets, wherein each packet is stored in a buffer and then transmitted via the I/O interface to a receiver, wherein the logic can vary a number of packets sent prior to the transmitter receiving an Acknowledgement (ACK) signal, and wherein the logic can vary a packet length of the number of packets.

Abstract translation: 描述了一种装置，包括：发射机; 耦合到发射机的输入输出（I / O）接口; 以及用于将数据分割成多个分组的逻辑，其中每个分组被存储在缓冲器中，然后经由所述I / O接口发送到接收机，其中所述逻辑可以改变在所述发射机接收之前发送的分组的数量 确认（ACK）信号，并且其中逻辑可以改变分组数量的分组长度。

公开(公告)号：US11513979B2

公开(公告)日：2022-11-29

申请号：US17187271

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20210209037A1

公开(公告)日：2021-07-08

申请号：US17187271

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20180300264A1

公开(公告)日：2018-10-18

申请号：US15706497

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Sean O. Stalley

IPC: G06F13/14 ,  G06F13/40 ,  G06F13/10

Abstract: Embodiments may include systems and methods for managing a function state of a device when the device is coupled to a processor through a computer bus. An apparatus for computing may include a processor coupled to a computer bus. A system driver may be executed by the processor to identify a function state of a device based on a feedback from a function status register in the device, when the device is coupled to the computer bus. A device may include an interface to be coupled to a computer bus, and a function status register coupled to the interface. The function status register may store information to indicate a function state of the device, and the function state may be accessible by a processor coupled to the function status register through the computer bus. Other embodiments may be described and/or claimed.

公开(公告)号：US09680758B2

公开(公告)日：2017-06-13

申请号：US14843883

申请日：2015-09-02

Applicant: Intel Corporation

Inventor： Sean O. Stalley

IPC: H04L12/801 ,  H04L12/805 ,  H04L12/841 ,  H04L12/835 ,  H04W28/02 ,  H04L5/00 ,  H04B1/02 ,  H04L12/26 ,  G06F3/06

CPC classification number: H04L47/39 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0656 ,  H04B1/02 ,  H04L5/0055 ,  H04L43/08 ,  H04L43/0864 ,  H04L43/0888 ,  H04L47/10 ,  H04L47/12 ,  H04L47/28 ,  H04L47/30 ,  H04L47/365 ,  H04W28/02

Abstract: Described is an apparatus which comprises: a transmitter; an input-output (I/O) interface coupled to the transmitter; and logic to split data for transmission into a plurality of packets, wherein each packet is stored in a buffer and then transmitted via the I/O interface to a receiver, wherein the logic can vary a number of packets sent prior to the transmitter receiving an Acknowledgement (ACK) signal, and wherein the logic can vary a packet length of the number of packets.

公开(公告)号：US11630480B2

公开(公告)日：2023-04-18

申请号：US15920249

申请日：2018-03-13

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Debendra Das Sharma ,  Daniel S. Froelich ,  Sean O. Stalley

IPC: G06F1/14 ,  G06F13/42 ,  H04B1/7073 ,  H04L69/14

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

公开(公告)号：US11593280B2

公开(公告)日：2023-02-28

申请号：US16564834

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Sean O. Stalley

IPC: G06F13/14 ,  G06N5/04 ,  G06F13/42

Abstract: Packets may be compressed based on predictive analyses. For example, in one embodiment, it is determined that an explicit value for a particular header field can be inferred by the receiver agent, a packet header is constructed that either omits the header field or includes a differential value for the header field in lieu of the explicit value for the header field. The packet header may be decompressed upon receipt by deriving the explicit value for the particular header field.

公开(公告)号：US20190391936A1

公开(公告)日：2019-12-26

申请号：US16564834

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Sean O. Stalley

IPC: G06F13/14 ,  G06F13/42 ,  G06N5/04

Abstract: Packets may be compressed based on predictive analyses. For example, in one embodiment, it is determined that an explicit value for a particular header field can be inferred by the receiver agent, a packet header is constructed that either omits the header field or includes a differential value for the header field in lieu of the explicit value for the header field. The packet header may be decompressed upon receipt by deriving the explicit value for the particular header field.