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公开(公告)号:US10756886B2
公开(公告)日:2020-08-25
申请号:US16045345
申请日:2018-07-25
申请人: Intel Corporation
IPC分类号: G06F16/25 , H04L9/08 , G06F3/06 , G06F9/50 , H04L29/06 , H04L29/08 , G06F16/2453 , H04L12/861 , G11C8/12 , G11C29/02 , H04L12/24 , G06F30/34 , G11C29/36 , G11C29/38 , G11C29/44 , G06F16/22 , G06F16/2455 , G06F12/02 , G06F12/14 , G06F13/16 , G06F15/173 , G06F13/40 , G06F13/42 , G06F9/448 , G06F9/28 , G06F15/16 , H04L12/703 , H04L12/743 , H04L12/801 , H04L12/803 , H04L12/935 , H04L12/931 , G06F9/4401 , G06F9/445 , G06F12/06 , G06F16/23 , G06F16/248 , G06F16/901 , G06F16/11 , G06F12/0802 , G06F12/1045
摘要: Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.
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公开(公告)号:US09621633B2
公开(公告)日:2017-04-11
申请号:US13836959
申请日:2013-03-15
申请人: Intel Corporation
发明人: Yadong Li , Anil Vasudevan , Linden Cornett
CPC分类号: H04L67/10 , G06F13/385
摘要: Generally, this disclosure relates to low latency networking. A system may include processor circuitry comprising at least one processor; memory circuitry configured to store an application, a receive queue and a networking stack comprising a network device driver; a network controller comprising a flow director, the network controller configured to couple the host device to at least one link partner and the flow director configured to store one or more selected received packets in the receive queue, the selecting based, at least in part, on a packet flow identifier; and a network device driver configured to identify the receive queue in response to a polling request comprising the packet flow identifier; poll the receive queue; and process each received packet stored in the receive queue.
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公开(公告)号:US09069722B2
公开(公告)日:2015-06-30
申请号:US13895917
申请日:2013-05-16
申请人: Intel Corporation
发明人: Yadong Li
IPC分类号: H04L12/56 , H04L29/02 , G06F15/173 , G06F13/00 , H04L12/701 , H04L12/861
CPC分类号: G06F15/17331 , H04L45/00 , H04L49/9036
摘要: The present disclosure describes a method and apparatus for network traffic processing in a non-uniform memory access architecture system. The method includes allocating a Tx/Rx Queue pair for a node, the Tx/Rx Queue pair allocated in a local memory of the node. The method further includes routing network traffic to the allocated Tx/Rx Queue pair. The method may include designating a core in the node for network traffic processing. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译: 本公开描述了用于非均匀存储器访问架构系统中的网络流量处理的方法和装置。 该方法包括为节点分配Tx / Rx队列对,Tx / Rx队列对分配在该节点的本地存储器中。 该方法还包括将网络业务路由到所分配的Tx / Rx队列对。 该方法可以包括指定节点中的核心用于网络流量处理。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。
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公开(公告)号:US11496419B2
公开(公告)日:2022-11-08
申请号:US17238893
申请日:2021-04-23
申请人: Intel Corporation
发明人: Shaopeng He , Cunming Liang , Jiang Yu , Ziye Yang , Ping Yu , Bo Cui , Jingjing Wu , Liang Ma , Hongjun Ni , Zhiguo Wen , Changpeng Liu , Anjali Singhai Jain , Daniel Daly , Yadong Li
IPC分类号: H04L47/56 , H04L49/9057 , H04L47/34 , H04L1/18 , H04L49/552 , H04L49/90
摘要: Examples described herein relate to a reliable transport protocol for packet transmission using an Address Family of an eXpress Data Path (AF_XDP) queue framework, wherein the AF_XDP queue framework is to provide a queue for received packet receipt acknowledgements (ACKs). In some examples, an AF_XDP socket is to connect a service with a driver for the network device, one or more queues are associated with the AF_XDP socket, and at least one of the one or more queues comprises a waiting queue for received packet receipt ACKs. In some examples, at least one of the one or more queues is to identify one or more packets for which ACKs have been received. In some examples, the network device is to re-transmit a packet identified by a descriptor in the waiting queue based on non-receipt of an ACK associated with the packet from a receiver.
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公开(公告)号:US11362904B2
公开(公告)日:2022-06-14
申请号:US16957626
申请日:2019-02-21
申请人: INTEL CORPORATION
发明人: Mrittika Ganguli , Dinesh Kumar , Robert Valiquette , Yadong Li , Mohan Kumar
摘要: Technologies for enhanced network discovery and configuration include a network with a fabric manager and multiple network devices. A network device requests platform information from a management controller and receives the platform information via a sideband interface. The network device broadcasts a discovery message indicative of the platform information on a link layer network. The fabric manager discovers the network topology with an enhanced link layer discovery protocol and creates a vPOD in the network. The vPOD includes an application network with multiple racks. The fabric manager creates a tagged network domain for the vPOD. The fabric manager sends an out-of-band configuration command to the network device with a tag associated with the vPOD. After receiving the out-of-band configuration command, the network device receives a packet, compares domain metadata of the packet to the tag received from the fabric manager, and routes the packet. Other embodiments are described and claimed.
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公开(公告)号:US20210194828A1
公开(公告)日:2021-06-24
申请号:US17114304
申请日:2020-12-07
申请人: Intel Corporation
发明人: Shaopeng He , Jingjing Wu , Haitao Kang , Yadong Li , Kun Tian
IPC分类号: H04L12/931 , H04L12/801 , G06F9/455
摘要: Methods and apparatus for smart switch centered next generation cloud infrastructure architectures. Smart server switches are implemented in place of Top of Rack (ToR) switches and other switches in cloud infrastructure that include programmable switch chips (e.g., P4 switch chips) that are programmed via data plane runtime code executing on the switch chips to implement data plane operations in hardware in the switches. Meanwhile, control plane operations are implemented in the server switches via software executing on one or more CPUs or are implemented via servers that are coupled to the server switches. The data plane runtime code is used to forward data traffic and storage traffic in hardware via the programmable switch chips in a manner that offloads forwarding to hardware in virtualized cloud environments.
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公开(公告)号:US10884968B2
公开(公告)日:2021-01-05
申请号:US16366496
申请日:2019-03-27
申请人: Intel Corporation
发明人: Matthew J. Adiletta , Bradley Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mirza , Jose Niell , Thomas E. Willis , William Duggan
摘要: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.
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8.
公开(公告)号:US20180088978A1
公开(公告)日:2018-03-29
申请号:US15280294
申请日:2016-09-29
申请人: Intel Corporation
发明人: Yadong Li , David Noeldner , Bryan E. Veal , Amber D. Huffman , Frank T. Hady
CPC分类号: G06F9/45558 , G06F13/28 , G06F2009/45579
摘要: Examples include techniques for input/output (I/O) access to physical memory or storage by a virtual machine (VM) or a container. Example techniques include use of a queue pair maintained at a controller for I/O access to the physical memory or storage. The queue pair including a submission queue and a completion queue. An assignment of a process address space identifier (PASID) to the queue pair facilitates I/O access to the physical memory or storage for a given VM or container.
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公开(公告)号:US20160321203A1
公开(公告)日:2016-11-03
申请号:US15008083
申请日:2016-01-27
申请人: Intel Corporation
CPC分类号: G06F13/24 , H04L69/165
摘要: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
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公开(公告)号:US09262354B2
公开(公告)日:2016-02-16
申请号:US14642967
申请日:2015-03-10
申请人: Intel Corporation
IPC分类号: G06F3/00 , G06F15/177 , G06F13/24
CPC分类号: G06F13/24 , H04L69/165
摘要: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
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