公开(公告)号：US06222762B1

公开(公告)日：2001-04-24

申请号：US08910947

申请日：1997-08-07

Applicant: Daniel C. Guterman ,  Yupin Kawing Fong

Inventor： Daniel C. Guterman ,  Yupin Kawing Fong

IPC: G11C1604

CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C16/3495 ,  G11C27/005 ,  G11C29/00 ,  G11C29/76 ,  G11C2211/5634 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract translation: 通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。 对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。 根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和 检测实际的最终数字数据。

公开(公告)号：US5965913A

公开(公告)日：1999-10-12

申请号：US844002

申请日：1997-04-18

Applicant: Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

Inventor： Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/01 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

公开(公告)号：US5910925A

公开(公告)日：1999-06-08

申请号：US65409

申请日：1998-04-23

Applicant: Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

Inventor： Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

IPC: G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885 ,  G11C2211/5634

Abstract: A novel memory structure in which memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract translation: 一种新颖的存储器结构，其中存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列形成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。

公开(公告)号：US5887145A

公开(公告)日：1999-03-23

申请号：US781539

申请日：1997-01-09

Applicant: Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

Inventor： Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/40 ,  H05K5/02

CPC classification number: G06F13/4068 ,  G06K19/07741 ,  H05K5/0265 ,  H05K5/0282

Abstract: A peripheral card having a Personal Computer ("PC") card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash "floppy" is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

公开(公告)号：US5776810A

公开(公告)日：1998-07-07

申请号：US193707

申请日：1994-02-09

Applicant: Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

Inventor： Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

IPC: G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885 ,  G11C2211/5634

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

Abstract translation: 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

公开(公告)号：US5712180A

公开(公告)日：1998-01-27

申请号：US607951

申请日：1996-02-28

Applicant: Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong

Inventor： Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885 ,  G11C2211/5634

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

公开(公告)号：US4302766A

公开(公告)日：1981-11-24

申请号：US1097

申请日：1979-01-05

Applicant: Daniel C. Guterman ,  Te-Long Chiu

Inventor： Daniel C. Guterman ,  Te-Long Chiu

IPC: G11C16/04 ,  H01L29/788 ,  H01L27/02 ,  B01J17/00

CPC classification number: H01L29/7885 ,  G11C16/0433

Abstract: A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.

Abstract translation: 电可擦除型的非易失性半导体存储器件采用浮置栅极，其通过在源极和漏极上施加高电压来编程，使得热电子穿过栅极氧化物。 浮动栅极通过电子隧道通过与控制栅极分离的擦除窗口放电。 非常小的单元尺寸由三重多晶硅结构提供。

公开(公告)号：US07898868B2

公开(公告)日：2011-03-01

申请号：US12499581

申请日：2009-07-08

Applicant: Daniel C. Guterman ,  Yupin Kawing Fong

Inventor： Daniel C. Guterman ,  Yupin Kawing Fong

IPC: G11C16/06

CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C16/3495 ,  G11C27/005 ,  G11C29/00 ,  G11C29/76 ,  G11C2211/5634 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract translation: 通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。 对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。 根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和 检测实际的最终数字数据。

公开(公告)号：US20100169561A1

公开(公告)日：2010-07-01

申请号：US12724286

申请日：2010-03-15

Applicant: Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

Inventor： Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

IPC: G06F13/12 ,  G06F12/02 ,  G06F13/00

CPC classification number: G06F13/4068 ,  G06K19/07741 ,  H05K5/0265 ,  H05K5/0282

Abstract: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

公开(公告)号：US20090286370A1

公开(公告)日：2009-11-19

申请号：US12510077

申请日：2009-07-27

Applicant: Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

Inventor： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8239

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

Abstract translation: 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。