公开(公告)号：US20240363398A1

公开(公告)日：2024-10-31

申请号：US18765006

申请日：2024-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng TANG ,  Fu-Chen CHANG ,  Cheng-Lin HUANG ,  Wen-Ming CHEN ,  Chun-Yen LO ,  Kuo-Chio LIU

IPC分类号： H01L21/768 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L21/76802 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/67011 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A semiconductor die is provided. The semiconductor die includes a substrate having a front surface, a rear surface opposite to the front surface, and a sidewall connected between the front surface and the rear surface. The sidewall includes a first primary segment immediately connected to the front surface, a second primary segment immediately connected to the rear surface, and a middle segment between the first primary segment and the second primary segment. The slope of the second primary segment is less than the slope of the first primary segment, and the slope of the middle segment is less than the slope of the second primary segment. Each of the first primary segment, the second primary segment, and the middle segment is a flat surface having a slope greater than 0 degrees relative to a line parallel to the front surface of the substrate.

公开(公告)号：US12125810B2

公开(公告)日：2024-10-22

申请号：US18190361

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

IPC分类号： H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/585 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/528

摘要： Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

公开(公告)号：US12094838B2

公开(公告)日：2024-09-17

申请号：US18355470

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jiun-Yu Chen ,  Chun-Lin Tsai ,  Yun-Hsiang Wang ,  Chia-Hsun Wu ,  Jiun-Lei Yu ,  Po-Chih Chen

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2225/06541

摘要： In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

公开(公告)号：US12074066B2

公开(公告)日：2024-08-27

申请号：US17846021

申请日：2022-06-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Yen Chiu

IPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/544 ,  H01L23/585 ,  H01L24/05 ,  H01L24/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/14 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/214 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/94 ,  H01L2224/214

摘要： An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

公开(公告)号：US12068263B2

公开(公告)日：2024-08-20

申请号：US18361227

申请日：2023-07-28

申请人： Taiwan Semiconductor Manfuacturing Company, Ltd.

发明人： Meng-Han Lin ,  Chia-En Huang

IPC分类号： H01L23/58 ,  H01L23/00 ,  H10B51/20

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L23/564 ,  H10B51/20

摘要： A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

公开(公告)号：US20240274593A1

公开(公告)日：2024-08-15

申请号：US18414750

申请日：2024-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： Seongmin SON ,  Seokho KIM ,  Sumin PARK ,  Kyuha LEE ,  Joohee JANG

IPC分类号： H01L27/02 ,  H01L23/13 ,  H01L23/58 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L23/13 ,  H01L23/585 ,  H01L2027/11875

摘要： A semiconductor device includes a first substrate structure and a second substrate structure stacked on the first substrate structure. The first substrate structure includes a plurality of first bonding pads in a first die region of a first substrate, a first passivation layer on the first substrate and exposing the first bonding pads, and a plurality of first dummy patterns in the first passivation layer in a first scribe region. The second substrate structure includes a plurality of second bonding pads in a second die region of a second substrate, a second passivation layer on the second substrate and exposing the second bonding pads, and a plurality of second dummy patterns in the second passivation layer in a second scribe region. The first bonding pad and the second bonding pad are directly bonded to each other.

公开(公告)号：US12040289B2

公开(公告)日：2024-07-16

申请号：US17412530

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hong-Seng Shue ,  Ming-Da Cheng ,  Ching-Wen Hsiao ,  Yao-Chun Chuang ,  Yu-Tse Su ,  Chen-Shien Chen

IPC分类号： H01L23/58 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/585 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

摘要： An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures. The edge seal ring structure may include a vertical stack of metallic ring structures that are free of aluminum and laterally surround the package-side bump structures and the redistribution interconnect structures.

公开(公告)号：US12002768B2

公开(公告)日：2024-06-04

申请号：US17458607

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Huang ,  Chih-Hao Chang ,  Po-Chun Lin ,  Chun-Ti Lu ,  Zheng-Gang Tsai ,  Shih-Wei Chen ,  Chia-Hung Liu ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC分类号： H01L23/58 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/585 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/2518

摘要： A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

公开(公告)号：US20240145408A1

公开(公告)日：2024-05-02

申请号：US18378858

申请日：2023-10-11

申请人： Infineon Technologies AG

发明人： Maria HEIDENBLUT ,  Michael GOROLL ,  Stefan KAISER ,  Sergey ANANIEV ,  Sabine BOGUTH ,  Gunther MACKH ,  Andreas BAUER ,  Georg Michael REUTHER

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/585

摘要： An electronic chip is disclosed. In one example, the electronic chip comprises a substrate comprising a central portion and an edge portion around at least part of the central portion. An active region is arranged in the central portion. A crack guiding structure combined with a crack stop structure is provided, both being arranged in the edge portion.

公开(公告)号：US11935827B2

公开(公告)日：2024-03-19

申请号：US17577794

申请日：2022-01-18

申请人： Saudi Arabian Oil Company ,  JGC Catalysts & Chemicals Ltd. ,  Japan Cooperation Center for Petroleum and Sustainable Energy

发明人： Omer Refa Koseoglu ,  Robert Peter Hodgkins ,  Koji Uchida

IPC分类号： B01J29/76 ,  B01J37/00 ,  B01J37/02 ,  B01J37/04 ,  B01J37/08 ,  H01L23/522 ,  H01L23/58 ,  H01L49/02

CPC分类号： H01L23/5223 ,  B01J29/76 ,  B01J35/617 ,  B01J35/643 ,  B01J35/647 ,  B01J35/651 ,  B01J37/0009 ,  B01J37/0207 ,  B01J37/04 ,  B01J37/082 ,  H01L23/585 ,  H01L28/87 ,  H01L28/91 ,  B01J2229/183 ,  B01J2229/42

摘要： Catalyst particles comprising one or more active metal components and methods for manufacturing such catalyst particles are provided. The particles are a composite of a granulating agent or binder material such as an inorganic oxide, and an ultra-stable Y (hereafter “USY”) zeolite in which some of the aluminum atoms in the framework are substituted with zirconium atoms and/or titanium atoms and/or hafnium atoms. The one or more active phase components are incorporated in a composite mixture of the inorganic oxide binder and the post-framework modified USY zeolite prior to forming the catalyst particles.