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    Method for synchronising analogue data at the output of a plurality of digital/analogue converters
    1.
    发明授权
    Method for synchronising analogue data at the output of a plurality of digital/analogue converters 有权

    公开(公告)号：US12040812B2

    公开(公告)日：2024-07-16

    申请号：US17636820

    申请日：2020-08-19

    Applicant: Teledyne e2v Semiconductors SAS

    Inventor： Quentin Béraud-Sudreau ,  Jérôme Ligozat ,  Rémi Laube ,  Marc Stackler

    IPC: H03M7/00 ,  G11C7/10 ,  H03K19/17736 ,  H03M1/12

    CPC classification number: H03M1/1255 ,  G11C7/1036 ,  H03K19/1774 ,  H03M1/1215

    Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

    BIT COUNTING CIRCUITS AND MEMORY DEVICES INCLUDING THE SAME
    2.
    发明公开
    BIT COUNTING CIRCUITS AND MEMORY DEVICES INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240233852A1

    公开(公告)日：2024-07-11

    申请号：US18406424

    申请日：2024-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Makoto Hirano ,  Jongmin Kim

    IPC: G11C29/32 ,  G11C7/10 ,  G11C29/12 ,  G11C29/20

    CPC classification number: G11C29/32 ,  G11C7/1036 ,  G11C29/1201 ,  G11C29/20

    Abstract: A nonvolatile memory device includes a control logic configured to generate a clock signal and a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers, a fail bit counting circuit configured to select one or more page buffers from among the plurality of page buffers, repeat the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the page buffers on which the fail bit counting operation is performed, and a predictor configured to generate a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.

    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    7.
    发明申请
    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开

    公开(公告)号：US20180122433A1

    公开(公告)日：2018-05-03

    申请号：US15855626

    申请日：2017-12-27

    Applicant: lntel Corporation

    Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

    IPC: G11C7/10 ,  G06F9/30

    CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    8.
    发明申请
    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开

    公开(公告)号：US20180122432A1

    公开(公告)日：2018-05-03

    申请号：US15855618

    申请日：2017-12-27

    Applicant: lntel Corporation

    Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

    IPC: G11C7/10 ,  G06F9/30

    CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    Data shift by elements of a vector in memory
    9.
    发明授权
    Data shift by elements of a vector in memory 有权

    公开(公告)号：US09928887B2

    公开(公告)日：2018-03-27

    申请号：US15457339

    申请日：2017-03-13

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096

    CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

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