公开(公告)号：US11611359B2

公开(公告)日：2023-03-21

申请号：US16987977

申请日：2020-08-07

Applicant: SK hynix Inc.

Inventor： Kyoung Lae Cho ,  Soo Jin Kim ,  Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin ,  Chenrong Xiong ,  Fan Zhang ,  Yu Cai ,  Abhiram Prabahkar

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

公开(公告)号：US09418892B2

公开(公告)日：2016-08-16

申请号：US15074885

申请日：2016-03-18

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Jin Ho Bin ,  Soo Jin Kim ,  Seung Ho Pyi

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76879 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/4991 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7828

Abstract: A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.

公开(公告)号：US11922064B2

公开(公告)日：2024-03-05

申请号：US17483119

申请日：2021-09-23

Applicant: SK hynix Inc.

Inventor： Soo Jin Kim ,  Seung Jin Park

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C7/1036 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A storage device can control the input/output of data at a high frequency. The storage device includes a memory device and a memory controller for controlling the memory device, and providing the memory device with a command. The memory device includes a memory unit, and an interface chip for performing a training operation in response to the command. The interface chip generates a shift signal according to a first data strobe signal provided from the memory controller, and stores, based on the shift signal, training data provided from the memory controller.

公开(公告)号：US11515897B2

公开(公告)日：2022-11-29

申请号：US16988026

申请日：2020-08-07

Applicant: SK hynix Inc.

Inventor： Kyoung Lae Cho ,  Soo Jin Kim ,  Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin ,  Chenrong Xiong ,  Fan Zhang ,  Yu Cai ,  Abhiram Prabahkar

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

公开(公告)号：US11996865B2

公开(公告)日：2024-05-28

申请号：US18185163

申请日：2023-03-16

Applicant: SK hynix Inc.

Inventor： Kyoung Lae Cho ,  Soo Jin Kim ,  Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin ,  Chenrong Xiong ,  Fan Zhang ,  Yu Cai ,  Abhiram Prabahkar

IPC: H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  H03M13/37 ,  H03M13/11

CPC classification number: H03M13/3707 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1076 ,  H03M13/1108 ,  H03M13/1111

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

公开(公告)号：US10741212B2

公开(公告)日：2020-08-11

申请号：US15620909

申请日：2017-06-13

Applicant: SK hynix Inc.

Inventor： Soo Jin Kim

IPC: G11B20/18 ,  H03M13/00 ,  H03M13/29 ,  H03M13/11 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15

Abstract: An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a “k”-bit original data in parallel and configured to perform a plurality of XOR operations to the “k”-bit original data to output a “(n−k)”-bit parity data. The “k”-bit original data and the “(n−k)”-bit parity data form an “n”-bit codeword, “k” denotes a natural number and “n” denotes a natural number which is greater than “k”.

公开(公告)号：US09324824B2

公开(公告)日：2016-04-26

申请号：US14324953

申请日：2014-07-07

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Jin Ho Bin ,  Soo Jin Kim ,  Seung Ho Pyi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L21/76847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76879 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/4991 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7828

Abstract: A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.

Abstract translation: 一种半导体器件，包括中心区域，位于中心区域两侧的侧面区域和形成在中心区域中的包括第一势垒图案的导电层，形成在第一阻挡图案中的材料图案，并且具有相对于 第一阻挡图案和形成在材料图案中的第二阻挡图案; 以及与导电层交替堆叠的绝缘层。