公开(公告)号：US11468921B2

公开(公告)日：2022-10-11

申请号：US17343027

申请日：2021-06-09

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G11C7/10 ,  G11C7/22

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

公开(公告)号：US11069387B2

公开(公告)日：2021-07-20

申请号：US16679582

申请日：2019-11-11

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G11C7/22 ,  G11C7/10

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command for controlling the memory device and output the command to the memory device. The interface circuit receives the command, transmits the received command to the semiconductor memory when the received command corresponds to the semiconductor memory, and performs a training operation of the interface circuit when the received command corresponds to the interface circuit and the received command is a specific command.

公开(公告)号：US11922064B2

公开(公告)日：2024-03-05

申请号：US17483119

申请日：2021-09-23

Applicant: SK hynix Inc.

Inventor： Soo Jin Kim ,  Seung Jin Park

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C7/1036 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A storage device can control the input/output of data at a high frequency. The storage device includes a memory device and a memory controller for controlling the memory device, and providing the memory device with a command. The memory device includes a memory unit, and an interface chip for performing a training operation in response to the command. The interface chip generates a shift signal according to a first data strobe signal provided from the memory controller, and stores, based on the shift signal, training data provided from the memory controller.

公开(公告)号：US11150838B2

公开(公告)日：2021-10-19

申请号：US16679601

申请日：2019-11-11

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/30 ,  G11C7/22

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command set in response to a host command and output the command set to the memory device. The interface circuit is configured to: receive the command set, transmit the received command set to the semiconductor memory, when the received command set corresponds to the semiconductor memory, perform a blocking operation so that the received command set is not transmitted to the semiconductor memory, when the received command set corresponds to the interface circuit, and perform an on-die termination operation, a ZQ calibration operation, or a driving force control operation of the interface circuit in response to the received command set corresponding to the interface circuit.

公开(公告)号：US11915790B2

公开(公告)日：2024-02-27

申请号：US17825837

申请日：2022-05-26

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G11C11/00 ,  G11C8/18 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C11/4076

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C16/32 ,  G11C2207/2272

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

公开(公告)号：US12119082B2

公开(公告)日：2024-10-15

申请号：US17968374

申请日：2022-10-18

Applicant: SK hynix Inc.

Inventor： Sang Geun Bae ,  Seung Jin Park

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C2207/2254 ,  G11C2207/2281

Abstract: A semiconductor system includes a first semiconductor device configured to output a clock and pattern data, configured to receive a strobe signal and output data, and configured to adjust a duty ratio of the strobe signal by comparing odd data and even data that are generated from the output data and the pattern data, in synchronization with the strobe signal and a second semiconductor device configured to store the pattern data in synchronization with the clock, configured to output the clock as the strobe signal by adjusting a duty ratio of the clock, and configured to output the stored pattern data as the output data.

公开(公告)号：US11972839B2

公开(公告)日：2024-04-30

申请号：US17873730

申请日：2022-07-26

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G11C16/04 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C16/32

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C16/32 ,  G11C2207/2272

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

公开(公告)号：US11430490B2

公开(公告)日：2022-08-30

申请号：US17343046

申请日：2021-06-09

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G11C7/10 ,  G11C7/22

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

公开(公告)号：US11139010B2

公开(公告)日：2021-10-05

申请号：US16992465

申请日：2020-08-13

Applicant: SK hynix Inc.

Inventor： Chang Kyun Park ,  Young Sik Koh ,  Seung Jin Park ,  Dong Hyun Lee

IPC: G11C8/00 ,  G11C8/18 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C11/4076

Abstract: Provided is a method for operating an interface circuit of a memory device. The method includes receiving a command from a controller; determining whether the command is for a semiconductor memory or the interface circuit, the semiconductor memory operatively coupled to the interface circuit; and when it is determined that the command is for the interface circuit, performing a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performing an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

公开(公告)号：US09324444B2

公开(公告)日：2016-04-26

申请号：US14092486

申请日：2013-11-27

Applicant: SK hynix Inc.

Inventor： Seung Jin Park

IPC: G11C7/10 ,  G11C16/30 ,  G11C7/22 ,  G11C5/14 ,  G06F3/06 ,  G11C16/32 ,  G06F13/16

CPC classification number: G11C16/30 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/1668 ,  G11C5/143 ,  G11C7/10 ,  G11C7/222 ,  G11C16/32 ,  Y02D10/14 ,  Y02D10/154

Abstract: A data storage device includes a nonvolatile memory device; and a controller electrically coupled with the nonvolatile memory device, and configured to control an operation of the nonvolatile memory device, wherein the controller is configured to change a frequency of an internal clock and a level of an internal voltage, according to whether data is being transmitted through a channel.

Abstract translation: 数据存储装置包括非易失性存储装置; 以及与所述非易失性存储器件电耦合并且被配置为控制所述非易失性存储器件的操作的控制器，其中所述控制器被配置为根据数据是否被改变内部时钟的频率和内部电压的电平 通过一个通道传输。