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1.发明授权公开(公告)号：US09501600B2
公开(公告)日：2016-11-22
申请号：US14051881
申请日：2013-10-11
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
CPC classification number: G06F17/5072 , G06F17/5068 , H01L27/0207 , H03K19/02
Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.
Abstract translation: 通过具有金属线的标称最小间距的预定制造工艺制造集成电路。 集成电路包括沿着第一方向延伸的多条金属线和多条金属线下的多个标准单元。 多个金属线在与第一方向垂直的第二方向上以标称最小间距的整数倍分开。 多个标准单元包括被配置为执行预定功能并具有第一布局的第一标准单元和被配置为执行预定功能并且具有与第一布局不同的第二布局的第二标准单元。 第一和第二标准单元沿着第二方向具有单元高度（H），单元高度是标称最小间距的非整数倍。
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2.发明授权FinFET with an asymmetric source/drain structure and method of making same 有权具有不对称源极/漏极结构的FinFET及其制造方法公开(公告)号：US09231106B2
公开(公告)日：2016-01-05
申请号：US13790814
申请日：2013-03-08
Inventor： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Kuo-Nan Yang , Ming-Hsiang Song , Ta-Pen Guo
IPC: H01L29/78 , H01L21/336 , H01L27/088 , H01L27/092 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L21/20 , H01L29/66
CPC classification number: H01L29/0847 , H01L21/283 , H01L21/30604 , H01L21/823418 , H01L21/823431 , H01L21/823814 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L29/41758 , H01L29/66477 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/6681 , H01L29/7835 , H01L29/785
Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.
Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。 第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。
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公开(公告)号：US09158877B2
公开(公告)日：2015-10-13
申请号：US14015924
申请日：2013-08-30
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
CPC classification number: G06F17/5072 , G06F17/5068 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L29/785
Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.
Abstract translation: 半导体结构包括第一有源区结构，围绕第一有源区结构的隔离结构，第一多晶硅结构，第一金属结构和第二金属结构。 第一个多晶硅结构超过了第一个有源区结构。 第一金属结构直接在第一有源区结构的第一部分之上。 第二金属结构直接与第一多晶硅结构的一部分接触并与第一金属结构接触。
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4.发明申请FinFET with an Asymmetric Source/Drain Structure and Method of Making Same 有权具有不对称源极/漏极结构的FinFET及其制造方法公开(公告)号：US20140252477A1
公开(公告)日：2014-09-11
申请号：US13790814
申请日：2013-03-08
Inventor： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Kuo-Nan Yang , Ming-Hsiang Song , Ta-Pen Guo
CPC classification number: H01L29/0847 , H01L21/283 , H01L21/30604 , H01L21/823418 , H01L21/823431 , H01L21/823814 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L29/41758 , H01L29/66477 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/6681 , H01L29/7835 , H01L29/785
Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.
Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。 第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。
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公开(公告)号：US12211793B2
公开(公告)日：2025-01-28
申请号：US17866880
申请日：2022-07-18
Inventor： Ni-Wan Fan , Ting-Wei Chiang , Cheng-I Huang , Jung-Chan Yang , Hsiang-Jen Tseng , Lipen Yuan , Chi-Yu Lu
IPC: H01L23/528 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L23/535 , H01L27/02 , H01L27/088 , H01L29/66 , H01L27/118
Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10289789B2
公开(公告)日：2019-05-14
申请号：US15601697
申请日：2017-05-22
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
IPC: G06F17/50 , H01L27/02 , H01L21/768 , H01L27/118
Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
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公开(公告)号：US09098668B2
公开(公告)日：2015-08-04
申请号：US14092697
申请日：2013-11-27
Inventor： Li-Chun Tien , Hui-Zhong Zhuang , Ting-Wei Chiang , Hsiang-Jen Tseng , Wei-Yu Chen
IPC: G06F17/50
CPC classification number: G06F17/5072 , H01L2924/0002 , H01L2924/00
Abstract: A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The cell layout includes an upper cell boundary, a lower cell boundary, a first cell boundary and a second cell boundary. The upper cell boundary and the lower cell boundary extend along X direction. The first cell boundary and the second cell boundary extend along Y direction. The upper cell boundary is defined in a portion of the first metal line. The lower cell boundary is defined in a portion of the second metal line. The first cell boundary is defined in a portion of the first jog and a portion of the second jog.
Abstract translation: 电池布局包括用于VDD电力的第一金属线，其包括到第一金属线并且垂直于第一金属线的第一点动耦合。 第二金属线用于VSS电力，并且包括与第二金属线垂直的第二点动耦合。 单元布局包括上单元边界，下单元边界，第一单元边界和第二单元边界。 上单元边界和下单元边界沿着X方向延伸。 第一个单元边界和第二个单元边界沿Y方向延伸。 上电池边界限定在第一金属线的一部分中。 下部单元边界被限定在第二金属线的一部分中。 第一单元边界被限定在第一点动的一部分和第二点动的一部分中。
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公开(公告)号：US20150149976A1
公开(公告)日：2015-05-28
申请号：US14092697
申请日：2013-11-27
Inventor： Li-Chun Tien , Hui-Zhong Zhuang , Ting-Wei Chiang , Hsiang-Jen Tseng , Wei-Yu Chen
IPC: G06F17/50
CPC classification number: G06F17/5072 , H01L2924/0002 , H01L2924/00
Abstract: A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The cell layout includes an upper cell boundary, a lower cell boundary, a first cell boundary and a second cell boundary. The upper cell boundary and the lower cell boundary extend along X direction. The first cell boundary and the second cell boundary extend along Y direction. The upper cell boundary is defined in a portion of the first metal line. The lower cell boundary is defined in a portion of the second metal line. The first cell boundary is defined in a portion of the first jog and a portion of the second jog.
Abstract translation: 电池布局包括用于VDD电力的第一金属线，其包括到第一金属线并且垂直于第一金属线的第一点动耦合。 第二金属线用于VSS电力，并且包括与第二金属线垂直的第二点动耦合。 单元布局包括上单元边界，下单元边界，第一单元边界和第二单元边界。 上单元边界和下单元边界沿着X方向延伸。 第一个单元边界和第二个单元边界沿Y方向延伸。 上电池边界限定在第一金属线的一部分中。 下部单元边界被限定在第二金属线的一部分中。 第一单元边界被限定在第一点动的一部分和第二点动的一部分中。
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公开(公告)号：US20150035070A1
公开(公告)日：2015-02-05
申请号：US13955796
申请日：2013-07-31
Inventor： Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng , Wei-Yu Chen , Hui-Zhong Zhuang , Shang-Chih Hsieh , Li-Chun Tien
IPC: H01L27/092 , G06F17/50
CPC classification number: H01L27/092 , G06F17/5068 , H01L21/823437 , H01L27/0207 , H01L27/088
Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
Abstract translation: 集成电路布局包括第一有源区，第二有源区，第一PODE（OD边缘上的poly），第二PODE，第一晶体管和第二晶体管。 在第一有源区上的第一晶体管包括栅电极，源极区和漏极区。 在第二有源区上的第二晶体管包括栅电极，源极区和漏极区。 第一有源区和第二有源区相邻并且彼此电断开。 第一PODE和第二PODE位于第一有源区和第二有源区的相邻相邻边缘上。 第一和第二晶体管的源极区分别与第一PODE和第二PODE相邻。 第一PODE和第二PODE夹在第一晶体管和第二晶体管的源极区之间。
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公开(公告)号：US10380306B2
公开(公告)日：2019-08-13
申请号：US15356817
申请日：2016-11-21
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.
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