公开(公告)号：US20200161443A1

公开(公告)日：2020-05-21

申请号：US16751128

申请日：2020-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L21/67 ,  H01L27/088 ,  H01L21/285 ,  H01L21/28

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20180261459A1

公开(公告)日：2018-09-13

申请号：US15979938

申请日：2018-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen TSAI ,  Hsin-Yi LEE ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG ,  Ming-Hsing TSAI

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  C23C14/58 ,  C23C16/56 ,  C23C16/455

CPC classification number: H01L21/28105 ,  C23C14/58 ,  C23C14/5846 ,  C23C14/5873 ,  C23C16/02 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/56 ,  H01L21/02697 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76838 ,  H01L21/76886 ,  H01L29/4966 ,  H01L29/66795

Abstract: A system for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

公开(公告)号：US20180097085A1

公开(公告)日：2018-04-05

申请号：US15811374

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng WANG ,  Chi-Cheng HUNG ,  Da-Yuan LEE ,  Hsin-Yi LEE ,  Kuan-Ting LIU

IPC: H01L29/66 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

公开(公告)号：US20170110552A1

公开(公告)日：2017-04-20

申请号：US15178150

申请日：2016-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L21/67 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/67167 ,  H01L27/0886 ,  H01L29/517 ,  H01L29/518

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20230317446A1

公开(公告)日：2023-10-05

申请号：US17807513

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Sheng-Yung Chang ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/0217 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/42392 ,  H01L29/0669

Abstract: The present disclosure describes a method for forming a semiconductor device having a work function metal layer doped with tantalum to mitigate oxygen diffusion and improve device threshold voltage. The method includes forming a gate dielectric layer on a channel structure and forming a work function metal layer on the gate dielectric layer. The gate dielectric layer includes an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer. The method further includes doping the work function metal layer and the gate dielectric layer with tantalum.

公开(公告)号：US20220384267A1

公开(公告)日：2022-12-01

申请号：US17884518

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yi LEE ,  Kuan-Yu WANG ,  Cheng-Lung HUNG ,  Chi-On CHUI

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.

公开(公告)号：US20210376138A1

公开(公告)日：2021-12-02

申请号：US16887203

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US20170110551A1

公开(公告)日：2017-04-20

申请号：US15169566

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28556 ,  H01L21/67167 ,  H01L27/0886 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function metal layer is performed, where the fluorine-based treatment removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the fluorine-based treatment, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20240290659A1

公开(公告)日：2024-08-29

申请号：US18650026

申请日：2024-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yi LEE ,  Kuan-Yu WANG ,  Cheng-Lung HUNG ,  Chi-On CHUI

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L29/6681 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.

公开(公告)号：US20230015761A1

公开(公告)日：2023-01-19

申请号：US17875561

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.