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公开(公告)号：US20240355389A1
公开(公告)日：2024-10-24
申请号：US18760971
申请日：2024-07-01
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0033 , G11C2213/79
Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.
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公开(公告)号：US11942150B2
公开(公告)日：2024-03-26
申请号：US18054359
申请日：2022-11-10
Inventor： Chung-Cheng Chou , Zheng-Jun Lin , Pei-Ling Tseng
CPC classification number: G11C13/0038 , G11C13/003 , G11C2213/15 , G11C2213/79
Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.
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公开(公告)号：US11636896B2
公开(公告)日：2023-04-25
申请号：US17103239
申请日：2020-11-24
Inventor： Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
IPC: G11C13/00
Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
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公开(公告)号：US20220254412A1
公开(公告)日：2022-08-11
申请号：US17470849
申请日：2021-09-09
Inventor： Zheng-Jun Lin , Chin-I Su , Pei-Ling Tseng , Chung-Cheng Chou
IPC: G11C13/00
Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
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公开(公告)号：US20210096586A1
公开(公告)日：2021-04-01
申请号：US17010064
申请日：2020-09-02
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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Patent Agency Ranking
公开(公告)号：US12230320B2
公开(公告)日：2025-02-18
申请号：US18336395
申请日：2023-06-16
Inventor： Zheng-Jun Lin , Chin-I Su , Pei-Ling Tseng , Chung-Cheng Chou
IPC: G11C13/00
Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
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公开(公告)号：US12165705B2
公开(公告)日：2024-12-10
申请号：US18362863
申请日：2023-07-31
Inventor： Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
IPC: G11C13/00
Abstract: A method of operating a memory circuit includes generating a first current in response to a first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.
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公开(公告)号：US12131776B2
公开(公告)日：2024-10-29
申请号：US17695578
申请日：2022-03-15
Inventor： Zheng-Jun Lin , Chin-I Su , Chung-Cheng Chou , Chia-Fu Lee
IPC: G11C14/00 , G11C11/412 , G11C11/419 , H03K19/20 , G11C13/00 , H03K19/21
CPC classification number: G11C11/419 , G11C11/412 , G11C14/009 , H03K19/20 , G11C13/0026 , H03K19/21
Abstract: A memory device including a static random-access memory that includes two cross-coupled inverters and an access transistor having a gate connected to a word line. The memory device further includes one or more logic gates electrically coupled to the static random-access memory, and a non-volatile memory electrically coupled to the static random-access memory and configured to store data and be read using the static random-access memory, wherein the non-volatile memory is connected on one side to the access transistor and on another side to the two cross-coupled inverters.
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公开(公告)号：US20230335189A1
公开(公告)日：2023-10-19
申请号：US18336395
申请日：2023-06-16
Inventor： Zheng-Jun Lin , Chin-I Su , Pei-Ling Tseng , Chung-Cheng Chou
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/0038 , G11C13/003 , G11C13/0069 , G11C13/0026 , G11C2213/79
Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
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公开(公告)号：US11527285B2
公开(公告)日：2022-12-13
申请号：US17200416
申请日：2021-03-12
Inventor： Chung-Cheng Chou , Zheng-Jun Lin , Pei-Ling Tseng
Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.
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