公开(公告)号：US20210384192A1

公开(公告)日：2021-12-09

申请号：US17179469

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US10825810B2

公开(公告)日：2020-11-03

申请号：US16444683

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Jisu Kang ,  Jaehyun Park ,  Heonjong Shin ,  Yuri Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L21/8234

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

公开(公告)号：US12029024B2

公开(公告)日：2024-07-02

申请号：US17538064

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

公开(公告)号：US20230187358A1

公开(公告)日：2023-06-15

申请号：US18077281

申请日：2022-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonyoung Jung ,  Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Sooyeon Hong

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L27/0924 ,  H01L23/5283 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/66545 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823871

Abstract: An integrated circuit device includes: a substrate including a device area and a field area; active regions extending in a first direction in the device area; a first gate structure extending in a second direction intersecting the first direction in the device area and the field area; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact disposed on the first gate structure in the device area; and a second gate contact disposed on the second gate structure in the field area, wherein the first gate contact and the second gate contact are disposed at a level lower than an upper end of the first gate structure, and wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other.

公开(公告)号：US11469298B2

公开(公告)日：2022-10-11

申请号：US17101703

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhun Park ,  Deokhan Bae ,  Sungmin Kim ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L29/06 ,  H03K19/0185 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.

公开(公告)号：US20220320115A1

公开(公告)日：2022-10-06

申请号：US17538064

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

公开(公告)号：US11810957B2

公开(公告)日：2023-11-07

申请号：US17469361

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun Park ,  Deokhan Bae ,  Jin-Wook Kim ,  Yuri Lee ,  Inyeal Lee ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/41775 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

公开(公告)号：US10373953B2

公开(公告)日：2019-08-06

申请号：US15159464

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Jisu Kang ,  Jaehyun Park ,  Heonjong Shin ,  Yuri Lee

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

公开(公告)号：US11315926B2

公开(公告)日：2022-04-26

申请号：US17179469

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US20160343709A1

公开(公告)日：2016-11-24

申请号：US15159464

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Jisu Kang ,  Jaehyun Park ,  Heonjong Shin ,  Yuri Lee

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

Abstract translation: 半导体器件包括第一有源区和第二有源区，它们设置在半导体衬底中并且具有彼此面对的侧表面，设置在第一和第二有源区之间的隔离图案，设置在第一和第二有源区之间的半导体延伸层， 第二有源区，设置在第一有源区上的第一源/漏半导体层和设置在第二有源区上的第二源/漏半导体层。 第一和第二有源区的面对侧表面比隔离图案更靠近半导体延伸层。