公开(公告)号：US11810957B2

公开(公告)日：2023-11-07

申请号：US17469361

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun Park ,  Deokhan Bae ,  Jin-Wook Kim ,  Yuri Lee ,  Inyeal Lee ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/41775 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

公开(公告)号：US11757040B2

公开(公告)日：2023-09-12

申请号：US17569952

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um ,  Kwangyong Jang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41725 ,  H01L29/66545

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

公开(公告)号：US11575044B2

公开(公告)日：2023-02-07

申请号：US17179982

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238

Abstract: An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.

公开(公告)号：US11251306B2

公开(公告)日：2022-02-15

申请号：US17028191

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um ,  Kwangyong Jang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

公开(公告)号：US20210384192A1

公开(公告)日：2021-12-09

申请号：US17179469

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US11996364B2

公开(公告)日：2024-05-28

申请号：US17521080

申请日：2021-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal Lee ,  Dongbeen Kim ,  Jinwook Kim ,  Juhun Park ,  Deokhan Bae ,  Junghoon Seo ,  Myungyoon Um

IPC: H01L23/535 ,  H01L23/00 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L24/13 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2224/13025

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

公开(公告)号：US11327107B2

公开(公告)日：2022-05-10

申请号：US17023656

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun Park ,  Juhyun Kim ,  Deokhan Bae ,  Myungyoon Um

IPC: G01R31/26 ,  H01L21/66

Abstract: A method of testing a semiconductor device may include preparing a semiconductor substrate in which the semiconductor substrate includes a test element group including first and second test circuits, measuring first and second leakage currents in the first and second test circuits, respectively, and calculating leakage components by comparing the first and second leakage currents. Each of the first and second test circuits may include an active region, which is an upper portion of the semiconductor substrate, a gate electrode, which is configured to cross the active region and to extend in a first direction, and an active contact, which is on the active region, is spaced apart from the gate electrode, and extends in the first direction. The second test circuit may further include a first gate contact that is connected to the gate electrode and overlaps the active region in a vertical direction perpendicular to the substrate.

公开(公告)号：US11315926B2

公开(公告)日：2022-04-26

申请号：US17179469

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US20210391464A1

公开(公告)日：2021-12-16

申请号：US17179982

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417

Abstract: An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.

公开(公告)号：US12288749B2

公开(公告)日：2025-04-29

申请号：US18647307

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal Lee ,  Dongbeen Kim ,  Jinwook Kim ,  Juhun Park ,  Deokhan Bae ,  Junghoon Seo ,  Myungyoon Um

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.