Semiconductor package
    1.
    发明授权

    公开(公告)号:US10699983B2

    公开(公告)日:2020-06-30

    申请号:US16190825

    申请日:2018-11-14

    Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

    Image sensor package having multi-level stack structure

    公开(公告)号:US10541263B2

    公开(公告)日:2020-01-21

    申请号:US15797375

    申请日:2017-10-30

    Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

    Semiconductor device package
    4.
    发明授权

    公开(公告)号:US11309280B2

    公开(公告)日:2022-04-19

    申请号:US16923418

    申请日:2020-07-08

    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

    Electronic device including semiconductor device package

    公开(公告)号:US10727199B2

    公开(公告)日:2020-07-28

    申请号:US16002018

    申请日:2018-06-07

    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

    Semiconductor device
    6.
    发明授权

    公开(公告)号:US10038010B2

    公开(公告)日:2018-07-31

    申请号:US15593965

    申请日:2017-05-12

    Inventor: Yong-hoon Kim

    Abstract: A semiconductor device may include: a substrate; a first well region formed on the substrate; a second well region formed on the substrate, the first well region and the second well region extending in a first direction and being adjacent to each other in a second direction crossing the first direction; a first active region formed in the first well region; a first power region formed in the first well region, the first active region and the first power region being separate from each other in the first direction; a second active region array formed in the second well region; a second power region formed in the second well region, the second active region array and the second power region being separate from each other in the first direction; and a first dummy active region formed in the first well region between the first active region and the first power region, the first dummy active region being separate from the first active region and the first power region in the first direction.

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