公开(公告)号：US20220328520A1

公开(公告)日：2022-10-13

申请号：US17851310

申请日：2022-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

公开(公告)号：US20200227438A1

公开(公告)日：2020-07-16

申请号：US16837169

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

公开(公告)号：US20210391260A1

公开(公告)日：2021-12-16

申请号：US17459406

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US11107765B2

公开(公告)日：2021-08-31

申请号：US16853850

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US10211154B2

公开(公告)日：2019-02-19

申请号：US15350305

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US12274062B2

公开(公告)日：2025-04-08

申请号：US17729549

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younjeong Hwang ,  Minbum Kim ,  Hojun Seong ,  Sung-Hun Lee ,  Juneon Jin

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a source structure on a substrate, a stack structure including electrode layers and inter-electrode insulating layers, which are on the source structure and are alternately stacked, a vertical structure penetrating the stack structure and the source structure and being adjacent to the substrate, and a separation insulation pattern penetrating the stack structure and the source structure and being spaced apart from the vertical structure. The uppermost one of the inter-electrode insulating layers may include a first impurity injection region located at a first height from a top surface of the substrate. The stack structure may define a groove, in which the separation insulation pattern is located. An inner sidewall of the groove may define a recess region, which is located at the first height from the top surface of the substrate and is recessed toward the vertical structure.

公开(公告)号：US12183677B2

公开(公告)日：2024-12-31

申请号：US18526208

申请日：2023-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20240105604A1

公开(公告)日：2024-03-28

申请号：US18526208

申请日：2023-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US10204918B2

公开(公告)日：2019-02-12

申请号：US15285709

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

IPC: H01L27/148 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

公开(公告)号：US20180315772A1

公开(公告)日：2018-11-01

申请号：US16019119

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC: H01L27/11582 ,  H01L23/535 ,  H01L29/423 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42344

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.