公开(公告)号：US20250107185A1

公开(公告)日：2025-03-27

申请号：US18738197

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon Kim ,  Pankwi Park ,  Sungkeun Lim ,  Yuyeong Jo

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, a gate electrode on the plurality of semiconductor patterns, and extending in a first horizontal direction, a gate spacer disposed on a sidewall of the gate electrode in a second horizontal direction crossing the first horizontal direction, a source/drain pattern electrically connected to the plurality of semiconductor patterns, and including a first epitaxial pattern and a second epitaxial pattern on a side surface of the first epitaxial pattern in the second horizontal direction, and a protection pattern between at least one of the plurality of semiconductor patterns and the gate spacer and including a material having an etch selectivity with the first epitaxial pattern.

公开(公告)号：US20230402510A1

公开(公告)日：2023-12-14

申请号：US18100872

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu CHO ,  Jungtaek Kim ,  Moon Seung Yang ,  Sumin Yu ,  Seojin Jeong ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and a source/drain pattern on a side surface of the channel pattern, the source/drain pattern including a first section between a first level and a second level that is higher than the first level, a first variation section between the second level and a third level that is higher than the second level, and a second section between the third level and a fourth level that is higher than the third level, where a rate of change in germanium concentration in the first variation section in a first direction is greater than a rate of change in germanium concentration in each of the first section and the second section in the first direction, and a germanium concentration at each of the first level and the second level is greater than 0 at % and equal to or less than 10 at %.

公开(公告)号：US20230395662A1

公开(公告)日：2023-12-07

申请号：US18299086

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0673

Abstract: Semiconductor device may include an active region extending in a first direction, channel layers spaced apart from each other in a vertical direction, a gate structure extending on the active region and the channel layers to surround the channel layers and extending in a second direction, and a source/drain region on the active region adjacent to a side of the gate structure and contacting the plurality of channel layers. The source/drain region includes first to sixth epitaxial layers that are sequentially stacked in the vertical direction and have respective first to sixth germanium (Ge) concentrations. The first Ge concentration is lower than the second Ge concentration, the third Ge concentration is lower than the second Ge concentration and the fourth Ge concentration, and the fifth Ge concentration is lower than the fourth Ge concentration and the sixth Ge concentration.

公开(公告)号：US11177346B2

公开(公告)日：2021-11-16

申请号：US16666958

申请日：2019-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Sunguk Jang ,  Pankwi Park ,  Sangmoon Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).

公开(公告)号：US20210313322A1

公开(公告)日：2021-10-07

申请号：US17352763

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US12119347B2

公开(公告)日：2024-10-15

申请号：US18332298

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/26 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US20240297215A1

公开(公告)日：2024-09-05

申请号：US18658794

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0245 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20230215867A1

公开(公告)日：2023-07-06

申请号：US17966472

申请日：2022-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu CHO ,  Seokhoon Kim ,  Sanggil Lee ,  Pankwi Park

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate including a first region, a second region, and active regions extending in a first direction in the first region and in the second region; gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction; a plurality of channel layers spaced apart from each other in a third direction on active regions of the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and first source/drain regions and second source/drain regions in portions of the active regions that are recessed on both sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers, wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region, wherein an end portion of each of the first source/drain regions in the second direction in a plan view includes a tip region protruding in the second direction, and wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction.

公开(公告)号：US11688778B2

公开(公告)日：2023-06-27

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20230141852A1

公开(公告)日：2023-05-11

申请号：US17866966

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Jungtaek Kim ,  Dohyun Go ,  Pankwi Park ,  Dongsuk Shin ,  Namkyu Cho ,  Ryong Ha ,  Yang Xu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L21/823814 ,  H01L27/0922

Abstract: A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.