公开(公告)号：US20230317725A1

公开(公告)日：2023-10-05

申请号：US18332298

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/26 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US20210313322A1

公开(公告)日：2021-10-07

申请号：US17352763

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US09673279B2

公开(公告)日：2017-06-06

申请号：US15208007

申请日：2016-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongyun Lee ,  Kwang-Yong Yang ,  Keomyoung Shin ,  Jinwook Lee ,  Yongseok Lee

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/1033 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.

公开(公告)号：US11710738B2

公开(公告)日：2023-07-25

申请号：US17352763

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US11069681B2

公开(公告)日：2021-07-20

申请号：US16694706

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US12119347B2

公开(公告)日：2024-10-15

申请号：US18332298

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/26 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US09954061B2

公开(公告)日：2018-04-24

申请号：US15605698

申请日：2017-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongyun Lee ,  Kwang-Yong Yang ,  Keomyoung Shin ,  Jinwook Lee ,  Yongseok Lee

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/1033 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.