公开(公告)号：US20230040132A1

公开(公告)日：2023-02-09

申请号：US17741711

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Mo PARK ,  Kyu Bong CHOI ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyung In CHOI

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.

公开(公告)号：US20210098626A1

公开(公告)日：2021-04-01

申请号：US16910819

申请日：2020-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Da Hye KIM ,  Jae Mun KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Kyung In CHOI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

公开(公告)号：US20180158911A1

公开(公告)日：2018-06-07

申请号：US15887773

申请日：2018-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US20240105773A1

公开(公告)日：2024-03-28

申请号：US18332784

申请日：2023-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae Jun YU ,  Kyung In CHOI ,  Soon Wook JUNG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: There is provided a semiconductor device having improved performance and reliability. A semiconductor device comprises an active pattern extending in a first direction, a gate structure including a gate electrode, a gate spacer, and a gate capping pattern on the active pattern, the gate electrode extending in a second direction different from the first direction and the gate capping pattern including a lower gate capping pattern and an upper gate capping pattern; a source/drain pattern disposed on the active pattern; and a source/drain etch stop film disposed on an upper surface of the source/drain pattern and extending along a sidewall of the gate spacer. The lower gate capping pattern is disposed on an upper surface of the gate electrode and an upper surface of the gate spacer, and the source/drain etch stop film does not extend along a sidewall of the lower gate capping pattern.

公开(公告)号：US20220123145A1

公开(公告)日：2022-04-21

申请号：US17565650

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Da Hye KIM ,  Jae Mun KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Kyung In CHOI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

公开(公告)号：US20170373151A1

公开(公告)日：2017-12-28

申请号：US15424081

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US20160049336A1

公开(公告)日：2016-02-18

申请号：US14825556

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jong HAN ,  Bon Young KOO ,  Ki Yeon PARK ,  Jae Young PARK ,  Sun Young LEE ,  Kyung In CHOI

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/76224

Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成限定多个活性鳍片的沟槽，在多个活性鳍片上形成牺牲层，形成牺牲氧化物层，以及去除牺牲氧化物层。 形成牺牲氧化物层包括热处理牺牲层和多个活性鳍片的表面。