公开(公告)号：US11856770B2

公开(公告)日：2023-12-26

申请号：US17357213

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jaebok Baek ,  Giyong Chung ,  Jeehoon Han

IPC: H10B43/10 ,  H01L25/18 ,  H01L25/065 ,  H10B43/27 ,  H01L23/00

CPC classification number: H10B43/10 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

公开(公告)号：US11521981B2

公开(公告)日：2022-12-06

申请号：US17095821

申请日：2020-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangyoung Jung ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  H01L27/11565

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

公开(公告)号：US11641743B2

公开(公告)日：2023-05-02

申请号：US17501149

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US11616070B2

公开(公告)日：2023-03-28

申请号：US17155225

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoun Jo ,  Kohji Kanamori ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522

Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

公开(公告)号：US11177282B2

公开(公告)日：2021-11-16

申请号：US16921185

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US20240341099A1

公开(公告)日：2024-10-10

申请号：US18750042

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangyoung Jung ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC: H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region, a first electrode structure and a second electrode structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern is greater than a maximum width of the separation structure in the second direction.

公开(公告)号：US20220359563A1

公开(公告)日：2022-11-10

申请号：US17651633

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji Noh ,  Jung-Hwan Park ,  Kwangyoung Jung ,  Hyojoon Ryu ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

Abstract: Provided are three-dimensional semiconductor memory devices and electronic systems including the same. The device includes a substrate, stack structures each including interlayer dielectric layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, vertical channel structures which penetrate the stack structures, and a separation structure, which extends in a first direction across between the stack structures. The separation structure includes first parts each having a pillar shape, which extend in a third direction perpendicular to a top surface of the substrate, and second parts, which extend between the interlayer dielectric layers from sidewalls of the first parts and which connect the first parts to each other in the first direction. The separation structure is spaced apart from the vertical channel structures in a second direction which intersects the first direction.

公开(公告)号：US20220037347A1

公开(公告)日：2022-02-03

申请号：US17501149

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11565 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US20190035806A1

公开(公告)日：2019-01-31

申请号：US15955256

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseong Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US12185548B2

公开(公告)日：2024-12-31

申请号：US17318306

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Jaeryong Sim ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.