公开(公告)号：US11616078B2

公开(公告)日：2023-03-28

申请号：US17406245

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US11895827B2

公开(公告)日：2024-02-06

申请号：US17469469

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Youngjin Kwon ,  Dongseog Eun

IPC: H10B12/00

CPC classification number: H10B12/395 ,  H10B12/0383 ,  H10B12/50

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

公开(公告)号：US20220199626A1

公开(公告)日：2022-06-23

申请号：US17469469

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Youngjin Kwon ,  Dongseog Eun

IPC: H01L27/108

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

公开(公告)号：US11956965B2

公开(公告)日：2024-04-09

申请号：US17212029

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Giyong Chung ,  Jaehyung Kim

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device and an electronic system, the memory device including a substrate; a ground selection line on the substrate, a cutting portion cutting the ground selection line; a first insulation layer and a first word line stacked immediately above the ground selection line; and second insulation layers and second word lines alternately stacked on the first word line, wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, the first portion of the first word line has a first thickness, and the second portion of the first word line has a second thickness less than the first thickness.

公开(公告)号：US11856770B2

公开(公告)日：2023-12-26

申请号：US17357213

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jaebok Baek ,  Giyong Chung ,  Jeehoon Han

IPC: H10B43/10 ,  H01L25/18 ,  H01L25/065 ,  H10B43/27 ,  H01L23/00

CPC classification number: H10B43/10 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

公开(公告)号：US20220149060A1

公开(公告)日：2022-05-12

申请号：US17362903

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAERYONG SIM ,  Giyong Chung ,  Dongsik Oh ,  Jeehoon Han

IPC: H01L27/11529 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate, electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.

公开(公告)号：US11114461B2

公开(公告)日：2021-09-07

申请号：US16700059

申请日：2019-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US12185548B2

公开(公告)日：2024-12-31

申请号：US17318306

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Jaeryong Sim ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

公开(公告)号：US20240138141A1

公开(公告)日：2024-04-25

申请号：US18402144

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Youngjin Kwon ,  Dongseog Eun

IPC: H10B12/00

CPC classification number: H10B12/395 ,  H10B12/0383 ,  H10B12/50

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

公开(公告)号：US11844214B2

公开(公告)日：2023-12-12

申请号：US17362903

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Giyong Chung ,  Dongsik Oh ,  Jeehoon Han

IPC: H10B41/41 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/41 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.