公开(公告)号：US20180233567A1

公开(公告)日：2018-08-16

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/485 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US10276675B2

公开(公告)日：2019-04-30

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/78 ,  H01L29/66

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US20170365555A1

公开(公告)日：2017-12-21

申请号：US15389856

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hun Choi ,  Jeong-Ik Kim ,  Chul-Sung Kim ,  Jae-Eun Lee ,  Sang-Jin Hyun

IPC: H01L23/535 ,  H01L23/532 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

Abstract: Semiconductor devices may include a structure on a substrate, an insulating interlayer, a metal silicide pattern, a first barrier pattern, a second barrier pattern and a metal pattern. The structure may include silicon. The insulating interlayer may include a contact hole exposing a surface of the structure. The metal silicide pattern may be in a lower portion of the contact hole, and the metal silicide pattern may directly contact the exposed surface of the structure. The first barrier pattern may directly contact an upper surface of the metal silicide pattern and a sidewall of the contact hole. The first barrier pattern may include a metal nitride. The second barrier pattern may be formed on the first barrier pattern. The second barrier pattern may include a metal nitride. The metal pattern may be formed on the second barrier pattern. The metal pattern may be in the contact hole.