公开(公告)号：US09524879B2

公开(公告)日：2016-12-20

申请号：US14669221

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Su Lee ,  Young-Wook Park ,  Hee-Sook Park ,  Dong-Bok Lee ,  Jong-Myeong Lee

IPC: H01L21/336 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/31111 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76895 ,  H01L27/10855 ,  H01L29/4236 ,  H01L29/78

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract translation: 半导体器件以及半导体器件的制造方法包括：形成贯穿层间绝缘层的接触孔，露出限定接触孔的底面的导体，形成填充接触孔的牺牲层，形成与第一沟槽重叠的部分 通过去除所述牺牲层的至少一部分，形成填充所述第一沟槽的间隔物，通过去除所述牺牲层的剩余部分形成第二沟槽，以及使用以下方式形成填充所述接触孔和所述第二沟槽的金属电极： 无电镀。

公开(公告)号：US20160064277A1

公开(公告)日：2016-03-03

申请号：US14674332

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun PARK ,  Dong-Hyun Im ,  Soon-Gun Lee ,  Jong-Myeong Lee ,  Han-Jin Lim

IPC: H01L21/768 ,  H01L49/02

CPC classification number: H01L21/76837 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L29/413 ,  H01L2221/1094

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract translation: 制造半导体器件的方法可以包括形成引导图案，其暴露基底图案，通过执行第一纳米线生长工艺在基底图案上形成第一纳米线，在第一纳米线之间形成第一模制绝缘层， 去除纳米线，并在孔中形成包括导电材料的第一电极。

公开(公告)号：US09754826B2

公开(公告)日：2017-09-05

申请号：US15155478

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-Hee Nam ,  In-Sun Park ,  Jong-Myeong Lee

IPC: H01L21/763 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11529 ,  H01L21/288 ,  H01L27/108

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

公开(公告)号：US20150061074A1

公开(公告)日：2015-03-05

申请号：US14340923

申请日：2014-07-25

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Hyun-Suk Lee ,  Tae-Kyun Kim ,  Jin-Su Lee ,  Dong-Kyun Park ,  Jong-Myeong Lee

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/90

Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.

Abstract translation: 半导体器件在衬底上包括MIM电容器。 MIM电容器包括电介质区域和在电介质区域的相对侧上的第一和第二电极。 第一电极和第二电极中的至少一个，例如上电极，包括氧离子阻挡材料，例如氧原子，其浓度在远离电介质区域的方向上减小。 第一和第二电极中的至少一个可以包括具有第一浓度的氧扩散阻挡材料的第一层和第一层上的第二层，并且具有小于第一浓度的第二浓度的氧扩散阻挡材料。 第一和第二电极中的至少一个还可以包括第二层上的第三层，并且具有小于第二浓度的氧扩散阻塞材料的浓度。

公开(公告)号：US09543196B2

公开(公告)日：2017-01-10

申请号：US14674332

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Park ,  Dong-Hyun Im ,  Soon-Gun Lee ,  Jong-Myeong Lee ,  Han-Jin Lim

IPC: H01L21/20 ,  H01L21/82 ,  H01L21/768 ,  B82Y10/00 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L29/41

CPC classification number: H01L21/76837 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L29/413 ,  H01L2221/1094

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract translation: 制造半导体器件的方法可以包括形成引导图案，其暴露基底图案，通过执行第一纳米线生长工艺在基底图案上形成第一纳米线，在第一纳米线之间形成第一模制绝缘层， 去除纳米线，并在孔中形成包括导电材料的第一电极。

公开(公告)号：US09520460B2

公开(公告)日：2016-12-13

申请号：US14340923

申请日：2014-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Suk Lee ,  Tae-Kyun Kim ,  Jin-Su Lee ,  Dong-Kyun Park ,  Jong-Myeong Lee

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/90

Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.

Abstract translation: 半导体器件在衬底上包括MIM电容器。 MIM电容器包括电介质区域和在电介质区域的相对侧上的第一和第二电极。 第一电极和第二电极中的至少一个，例如上电极，包括氧离子阻挡材料，例如氧原子，其浓度在远离电介质区域的方向上减小。 第一和第二电极中的至少一个可以包括具有第一浓度的氧扩散阻挡材料的第一层和第一层上的第二层，并且具有小于第一浓度的第二浓度的氧扩散阻塞材料。 第一和第二电极中的至少一个还可以包括第二层上的第三层，并且具有小于第二浓度的氧扩散阻塞材料的浓度。

公开(公告)号：US08569862B2

公开(公告)日：2013-10-29

申请号：US13792996

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L33/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US20130193552A1

公开(公告)日：2013-08-01

申请号：US13792996

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。