公开(公告)号：US10943923B2

公开(公告)日：2021-03-09

申请号：US16574339

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Jeong ,  Jiwook Kwon ,  Sutae Kim ,  Hyelim Kim

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

公开(公告)号：US20230068716A1

公开(公告)日：2023-03-02

申请号：US17751093

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungju Kang ,  Raheel Azmat ,  Jiwook Kwon ,  Suhyeon Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H01L23/522 ,  H01L27/118

Abstract: A semiconductor device includes: a standard cell including a plurality of active patterns extending in a first direction, a gate structure intersecting the plurality of active patterns and extending in a second direction, and source/drain regions respectively provided on the plurality of active patterns positioned on both sides of the gate structure; a plurality of signal lines extending on the standard cell in the first direction, arranged in the second direction, and electrically connected to the standard cell; and first and second power straps extending on the standard cell in the first direction, electrically connected to some of the source/drain regions, and supplying power to the standard cell, wherein each of the first and second power straps is provided on the standard cell while provided on the same line as any one of the plurality of signal lines in the first direction.

公开(公告)号：US11348918B2

公开(公告)日：2022-05-31

申请号：US16864260

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/02

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US20230378155A1

公开(公告)日：2023-11-23

申请号：US18156494

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Suhyeong Choi ,  Jiwook Kwon ,  Chulhong Park

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394

Abstract: A semiconductor device includes first standard cells arranged in a first row on a substrate and respectively including a first base active region, second standard cells arranged in a second row adjacent to the first row and respectively including a second base active region, a power line extending in a first direction along a boundary between the first and second standard cells, and a device isolation layer on side surfaces of the first and second base active regions, wherein, in a plan view, the first standard cells and the second standard cells have a same cell height, the first base active region of each of the first standard cells includes a first active line having a first conductivity-type and a second active line having a second conductivity-type, the second base active region of each of the second standard cells includes a third active line having the first conductivity-type and a fourth active line having the second conductivity-type, the first active lines of the first standard cells arranged in the first row have a same first width, the third active lines of the second standard cells arranged in the second row have a same second width, and the first width is narrower than the second width.

公开(公告)号：US20230378027A1

公开(公告)日：2023-11-23

申请号：US18113133

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhyeong CHOI ,  Jiwook Kwon ,  Byungju Kang ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L23/48 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L23/5226

Abstract: A semiconductor device includes: a semiconductor substrate having power arrangement regions; a first interconnection structure disposed on the semiconductor substrate and including first interconnection patterns and power lines; a second interconnection structure disposed on the semiconductor substrate and including second interconnection patterns; and through-electrodes passing through each of the power arrangement regions and contacting the power lines, wherein the first interconnection patterns include first interconnection lines, wherein the power lines are disposed on a same height level as a first interconnection line, among the first interconnection lines, and are parallel to each other, wherein the power arrangement regions are parallel to each other, and wherein intersection regions, in which the power arrangement regions and the power lines intersect, include a plurality of first active intersection regions, one dummy intersection region, and a plurality of second active intersection regions, sequentially arranged.

公开(公告)号：US11688740B2

公开(公告)日：2023-06-27

申请号：US17740900

申请日：2022-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/02 ,  H10B10/00

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.