公开(公告)号：US20210257474A1

公开(公告)日：2021-08-19

申请号：US17039083

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Yeal LEE ,  Ju Youn KIM ,  Jin-Wook KIM ,  Ju Hun PARK ,  Deok Han BAE ,  Myung Yoon UM

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

公开(公告)号：US20180096688A1

公开(公告)日：2018-04-05

申请号：US15614001

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Wook KIM ,  Jae-Hyung Kim ,  Gi-Ha Woo

IPC: G10L15/28 ,  G10L17/00 ,  G06F3/16 ,  H05B37/02

Abstract: A voice recognition electronic device is provided which includes a housing including a first face that faces a first direction, a second face that faces a second direction opposite to the first direction, a third face disposed between the first face and the second face, and a translucent cover that forms at least a portion of the third face, a voice reception unit disposed below the first face of the housing and including a plurality of microphones that receive a voice input from a user, a light source unit disposed inside the housing to emit light, a driving unit connected to the light source unit to control the light source unit to move according to a preset operation, and a control unit that controls the driving unit in response to the voice input of the user, which is delivered from the voice reception unit.

公开(公告)号：US20220157955A1

公开(公告)日：2022-05-19

申请号：US17469361

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun PARK ,  Deokhan BAE ,  Jin-Wook KIM ,  Yuri LEE ,  Inyeal LEE ,  Yoonyoung JUNG

IPC: H01L29/417 ,  H01L27/092 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

公开(公告)号：US20190304972A1

公开(公告)日：2019-10-03

申请号：US16260275

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM ,  Jin-Wook KIM

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, an interlayer dielectric layer on the substrate and having a first opening and a second opening, a first gate pattern in the first opening and including a first work function pattern, a first conductive blocking pattern, a first blocking pattern, and a conductive pattern that are stacked, and a second gate pattern in the second opening. The second gate pattern includes a second work function pattern of a material the same as a material of the first work function pattern, and a second conductive blocking pattern on the second work function pattern and filling the second opening. The second conductive blocking pattern includes a material that is different from a material of the conductive pattern and is different from a material of the first blocking pattern.

公开(公告)号：US20190131417A1

公开(公告)日：2019-05-02

申请号：US15958061

申请日：2018-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Ki HONG ,  Ju Youn KIM ,  Jin-Wook KIM ,  Tae Eung YOON ,  Tae Won HA ,  Jung Hoon SEO ,  Seul Gi YUN

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

Abstract: A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and second active regions, and a gate electrode on the substrate and traversing the first active region, the second active region, and the field insulating layer. The gate electrode includes a first portion over the first active region, a second portion over the second active region, and a third portion in contact with the first and second portions. The gate electrode includes an upper gate electrode having first through third thicknesses in the first through third portions, respectively, where the third thickness is greater than the first thickness, and smaller than the second thickness.

公开(公告)号：US20220013649A1

公开(公告)日：2022-01-13

申请号：US17185466

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Yeal LEE ,  Yoon Young JUNG ,  Jin-Wook KIM ,  Deok Han BAE ,  Myung Yoon UM

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/51

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction intersecting the first direction on the active pattern, a gate spacer extending in the second direction along side walls of the gate electrode, an interlayer insulating layer contacting side walls of the gate spacer, a trench formed on the gate electrode in the interlayer insulating layer, a first capping pattern provided along side walls of the trench, at least one side wall of the first capping pattern having an inclined profile, and a second capping pattern provided on the first capping pattern in the trench.

公开(公告)号：US20180366583A1

公开(公告)日：2018-12-20

申请号：US16111854

申请日：2018-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gigwan PARK ,  Junggun YOU ,  DongSuk SHIN ,  Jin-Wook KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L27/092 ,  H01L27/11 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US20170117411A1

公开(公告)日：2017-04-27

申请号：US15288080

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gigwan PARK ,  Junggun YOU ,  DongSuk SHIN ,  Jin-Wook KIM

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L23/535 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.