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    Three-dimensional semiconductor memory device
    1.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11444094B2

    公开(公告)日：2022-09-13

    申请号：US16782737

    申请日：2020-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

    IPC: H01L27/11582 ,  H01L27/11556 ,  G11C5/02

    Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200303390A1

    公开(公告)日：2020-09-24

    申请号：US16782737

    申请日：2020-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

    Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

    Three-dimensional semiconductor memory device
    4.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11257841B2

    公开(公告)日：2022-02-22

    申请号：US16787195

    申请日：2020-02-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin-Kyu Kang ,  Woojae Jang ,  Changsub Lee ,  Sejun Park ,  Jaeduk Lee ,  Jung Hoon Lee

    IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78

    Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

    Semiconductor memory device and storage system including semiconductor memory device
    5.
    发明授权
    Semiconductor memory device and storage system including semiconductor memory device 有权

    公开(公告)号：US12154632B2

    公开(公告)日：2024-11-26

    申请号：US18545144

    申请日：2023-12-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye Ji Lee ,  Jin-Kyu Kang ,  Rae Young Lee ,  Se Jun Park ,  Jae Duk Lee ,  Gu Yeon Han

    IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

    Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

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