公开(公告)号：US20220077040A1

公开(公告)日：2022-03-10

申请号：US17318227

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi JIN ,  Gyuho KANG ,  Solji SONG ,  Un-Byoung KANG ,  Ju-Il CHOI

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

公开(公告)号：US20220059466A1

公开(公告)日：2022-02-24

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20210335688A1

公开(公告)日：2021-10-28

申请号：US17035145

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji SONG ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20130334656A1

公开(公告)日：2013-12-19

申请号：US13797655

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi JIN ,  Jeong-woo PARK ,  Ju-il Choi

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/293 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.

Abstract translation: 提供电连接结构及其制造方法。 该结构可以包括：衬底，其包括具有接合焊盘的接合焊盘区域和设置有保险丝的熔断器区域，设置在衬底上的绝缘层，并且包括露出焊盘的焊盘开口和暴露熔丝区域的保险丝开口 设置在所述焊盘区域中并且电连接到所述焊盘的连接端子，以及设置在所述绝缘层上的保护层，所述保护层包括设置在所述焊盘区域内的第一保护层和所述熔丝开口中的第二保护层。

公开(公告)号：US20240312894A1

公开(公告)日：2024-09-19

申请号：US18668974

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20220068779A1

公开(公告)日：2022-03-03

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Jeonggi JIN ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US20220037248A1

公开(公告)日：2022-02-03

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20240312923A1

公开(公告)日：2024-09-19

申请号：US18677075

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20230238316A1

公开(公告)日：2023-07-27

申请号：US18189834

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Teahwa JEONG ,  Jeonggi JIN

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0652

Abstract: A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

公开(公告)号：US20230111136A1

公开(公告)日：2023-04-13

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji Song ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.