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公开(公告)号：US11037610B2
公开(公告)日：2021-06-15
申请号：US16210303
申请日：2018-12-05
Applicant: SK hynix Inc.
Inventor： Seunggyu Jeong , Jung Hyun Kwon , Wongyu Shin , Do Sun Hong
Abstract: A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.
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公开(公告)号：US11048586B2
公开(公告)日：2021-06-29
申请号：US16883783
申请日：2020-05-26
Applicant: SK hynix Inc.
Inventor： Won Gyu Shin , Jung Hyun Kwon , Jin Woong Suh , Do Sun Hong
Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.
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3.发明授权公开(公告)号：US10475522B2
公开(公告)日：2019-11-12
申请号：US15821155
申请日：2017-11-22
Applicant: SK hynix Inc.
Inventor： Donggun Kim , Yong Ju Kim , Do Sun Hong
Abstract: A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.
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公开(公告)号：US10223255B2
公开(公告)日：2019-03-05
申请号：US15821291
申请日：2017-11-22
Applicant: SK hynix Inc.
Inventor： Donggun Kim , Yong Ju Kim , Do Sun Hong
Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.
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公开(公告)号：US20180260321A1
公开(公告)日：2018-09-13
申请号：US15821291
申请日：2017-11-22
Applicant: SK hynix Inc.
Inventor： Donggun Kim , Yong Ju Kim , Do Sun Hong
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F12/1466 , G06F2212/1052 , G06F2212/7201 , G06F2212/7211
Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.
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Patent Agency Ranking
公开(公告)号：US11005599B2
公开(公告)日：2021-05-11
申请号：US16731461
申请日：2019-12-31
Applicant: SK hynix Inc.
Inventor： Do Sun Hong , Seung Gyu Jeong
Abstract: A data transmission system includes a data transmitter and a data receiver. The data transmitter outputs ‘N’-bit transmission data (where ‘N’ denotes a natural number which is equal to or greater than two). The data receiver receives the ‘N’-bit transmission data through ‘N’-number of data transmission lines. The data receiver transmits a re-transmission request signal to the data transmitter when the ‘N’-bit transmission data inputted to the data receiver are erroneous data. The data transmitter divides the ‘N’-bit transmission data in response to the re-transmission request signal and operates in a first data re-transmission mode so that the divided transmission data are resent, together with first ground data, to the data receiver.
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7.发明授权公开(公告)号：US10438655B2
公开(公告)日：2019-10-08
申请号：US15822718
申请日：2017-11-27
Applicant: SK hynix Inc.
Inventor： Donggun Kim , Jung Hyun Kwon , Yong Ju Kim , Do Sun Hong
IPC: G11C11/00 , G11C11/56 , G11C16/04 , G11C16/10 , G11C7/10 , G06F12/02 , G11C16/08 , G11C13/00 , G11C16/34 , G11C7/12 , G11C8/08
Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.
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公开(公告)号：US10310972B1
公开(公告)日：2019-06-04
申请号：US16271431
申请日：2019-02-08
Applicant: SK hynix Inc.
Inventor： Donggun Kim , Yong Ju Kim , Do Sun Hong
Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.
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公开(公告)号：US11036597B2
公开(公告)日：2021-06-15
申请号：US16212302
申请日：2018-12-06
Applicant: SK hynix Inc.
Inventor： Wongyu Shin , Jung Hyun Kwon , Seunggyu Jeong , Do Sun Hong
Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.
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10.发明申请公开(公告)号：US20190385693A1
公开(公告)日：2019-12-19
申请号：US16203362
申请日：2018-11-28
Applicant: SK hynix Inc.
Inventor： Wongyu Shin , Jung Hyun Kwon , Seunggyu Jeong , Do Sun Hong
IPC: G11C29/42 , G06F11/10 , G11C11/409 , G11C11/16 , H03M13/11
Abstract: A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.
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