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公开(公告)号：US20230066632A1
公开(公告)日：2023-03-02
申请号：US18047614
申请日：2022-10-18
发明人： Donghun Lee , Daesik Moon , Young-Soo Sohn , Young-Hoon Son , Ki-Seok Oh , Changkyo Lee , Hyun-Yoon Cho , Kyung-Soo Ha , Seokhun Hyun
摘要： A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
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公开(公告)号：US20220157845A1
公开(公告)日：2022-05-19
申请号：US17443448
申请日：2021-07-26
发明人： MIN JAE LEE , Jin Do Byun , Young-Hoon Son , Young Don Choi , Pan Suk Kwak , Myung Hun Lee , Jung Hwan Choi
IPC分类号： H01L27/11573 , H01L27/11519 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L23/522 , H01L23/528 , G11C16/08
摘要： A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.
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公开(公告)号：US11508420B2
公开(公告)日：2022-11-22
申请号：US17355765
申请日：2021-06-23
发明人： Donghun Lee , Daesik Moon , Young-Soo Sohn , Young-Hoon Son , Ki-Seok Oh , Changkyo Lee , Hyun-Yoon Cho , Kyung-Soo Ha , Seokhun Hyun
摘要： A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
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公开(公告)号：US10692554B2
公开(公告)日：2020-06-23
申请号：US16721131
申请日：2019-12-19
发明人： Young-Hoon Son , Si-Hong Kim , Chang-Kyo Lee , Jung-Hwan Choi , Kyung-Soo Ha
摘要： A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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公开(公告)号：US10665558B2
公开(公告)日：2020-05-26
申请号：US16036198
申请日：2018-07-16
发明人： Sihong Kim , Young-Hoon Son , Taeyoung Oh , Kyung-Soo Ha
摘要： A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.
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公开(公告)号：US11687114B2
公开(公告)日：2023-06-27
申请号：US17145211
申请日：2021-01-08
发明人： Junyoung Park , Young-Hoon Son , Hyun-Yoon Cho , Youngdon Choi , Junghwan Choi
IPC分类号： G06F1/06 , G11C11/406 , G11C11/403 , G06F13/40
CPC分类号： G06F1/06 , G06F13/4022 , G11C11/403 , G11C11/40607
摘要： Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
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公开(公告)号：US11461176B2
公开(公告)日：2022-10-04
申请号：US17398158
申请日：2021-08-10
摘要： A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.
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8.发明授权公开(公告)号：US11169711B2
公开(公告)日：2021-11-09
申请号：US16524749
申请日：2019-07-29
发明人： Seong-Il O , Nam Sung Kim , Young-Hoon Son , Chan-Kyung Kim , Ho-Young Song , Jung Ho Ahn , Sang-Joon Hwang
摘要： A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
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公开(公告)号：US11475930B2
公开(公告)日：2022-10-18
申请号：US17141357
申请日：2021-01-05
发明人： Young-Hoon Son , Si-Hong Kim , Chang-Kyo Lee , Jung-Hwan Choi , Kyung-Soo Ha
IPC分类号： H03K19/003 , G11C7/24 , H03H7/38 , G11C7/10
摘要： A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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公开(公告)号：US11244926B2
公开(公告)日：2022-02-08
申请号：US16105202
申请日：2018-08-20
发明人： Young-Hoon Son , Jung-Hwan Choi , Seok-Hun Hyun
IPC分类号： H01L25/00 , H01L25/065 , H01L23/00 , H01L25/10
摘要： A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.
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