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公开(公告)号：US10692554B2
公开(公告)日：2020-06-23
申请号：US16721131
申请日：2019-12-19
发明人： Young-Hoon Son , Si-Hong Kim , Chang-Kyo Lee , Jung-Hwan Choi , Kyung-Soo Ha
摘要： A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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公开(公告)号：US11475930B2
公开(公告)日：2022-10-18
申请号：US17141357
申请日：2021-01-05
发明人： Young-Hoon Son , Si-Hong Kim , Chang-Kyo Lee , Jung-Hwan Choi , Kyung-Soo Ha
IPC分类号： H03K19/003 , G11C7/24 , H03H7/38 , G11C7/10
摘要： A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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公开(公告)号：US10916279B2
公开(公告)日：2021-02-09
申请号：US16848364
申请日：2020-04-14
发明人： Young-Hoon Son , Si-Hong Kim , Chang-Kyo Lee , Jung-Hwan Choi , Kyung-Soo Ha
摘要： A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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公开(公告)号：US10566038B2
公开(公告)日：2020-02-18
申请号：US15918526
申请日：2018-03-12
发明人： Young-Hoon Son , Si-Hong Kim , Chang-Kyo Lee , Jung-Hwan Choi , Kyung-Soo Ha
摘要： A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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公开(公告)号：US09685218B2
公开(公告)日：2017-06-20
申请号：US15236895
申请日：2016-08-15
发明人： Young-Soo Sohn , Chul-Woo Park , Si-Hong Kim , Kwang-Il Park , Jae-Youn Youn
IPC分类号： G11C7/10 , G11C11/406 , G11C11/4076 , G11C11/408
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4087
摘要： A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.
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公开(公告)号：US09536586B2
公开(公告)日：2017-01-03
申请号：US14514416
申请日：2014-10-15
发明人： Young-Soo Sohn , Chul-Woo Park , Si-Hong Kim , Kwang-Il Park , Jae-Youn Youn
IPC分类号： G11C7/10 , G11C11/406 , G11C11/408 , G11C11/4076
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4087
摘要： A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.
摘要翻译： 存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。 存储单元阵列包括多个存储单元行。 集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。 当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。 存储器件有效地降低了数据丢失率。
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