公开(公告)号：US20240204098A1

公开(公告)日：2024-06-20

申请号：US18592332

申请日：2024-02-29

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20240055301A1

公开(公告)日：2024-02-15

申请号：US18336203

申请日：2023-06-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yudai HIGA ,  Atsushi SAKAI ,  Yotaro GOTO

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L27/088 ,  H01L21/823475

Abstract: A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.

公开(公告)号：US20210074816A1

公开(公告)日：2021-03-11

申请号：US16996351

申请日：2020-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20240290881A1

公开(公告)日：2024-08-29

申请号：US18638883

申请日：2024-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0274 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/4916

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20230118274A1

公开(公告)日：2023-04-20

申请号：US17887156

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Katsumi EIKYU ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.

公开(公告)号：US20210217888A1

公开(公告)日：2021-07-15

申请号：US17216136

申请日：2021-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20250015138A1

公开(公告)日：2025-01-09

申请号：US18892925

申请日：2024-09-23

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20240387648A1

公开(公告)日：2024-11-21

申请号：US18616917

申请日：2024-03-26

Applicant: Renesas Electronics Corporation

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Tomoya NISHIMURA

IPC: H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423

Abstract: Performance of a semiconductor device is improved. In a semiconductor substrate (SUB), a trench TR1 and a trench TR2 are formed so as to reach a predetermined depth from an upper surface (TS) of the semiconductor substrate (SUB). A field-plate electrode (FP) is formed at a lower portion of the trench TR1, and a gate-electrode GE1 is formed at an upper portion of the trench TR1. A gate electrode GE2 is formed inside the trench TR2. The depth of the trench TR1 is deeper than the depth of the trench TR2. The trench TR1 is surrounded by the trench TR2 in plan view.

公开(公告)号：US20240113218A1

公开(公告)日：2024-04-04

申请号：US18353250

申请日：2023-07-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoya NISHIMURA ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A first trench extending in a Y direction is formed in each of a semiconductor substrate located in a cell region and the semiconductor substrate located in an outer peripheral region. A second trench is formed in the semiconductor substrate in the outer peripheral region so as to surround the cell region in a plan view. A p-type body region is formed in the semiconductor substrate in each region. A plurality of p-type floating regions is formed in the semiconductor substrate in the outer peripheral region. A field plate electrode is formed at a lower portion of each of the first trench and the second trench. A gate electrode is formed at an upper portion of the first trench located in the cell region. A floating gate electrode is formed at an upper portion of each of the first trench located in the outer peripheral region and the second trench.

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.