公开(公告)号：US12255381B2

公开(公告)日：2025-03-18

申请号：US17652328

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01Q1/22 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00 ,  H01L25/10

Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.

公开(公告)号：US11380678B2

公开(公告)日：2022-07-05

申请号：US16899811

申请日：2020-06-12

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Je-Hsiung Lan ,  Jonghae Kim

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/66

Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

公开(公告)号：US11689181B2

公开(公告)日：2023-06-27

申请号：US16884891

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Je-Hsiung Lan ,  Ranadeep Dutta ,  Milind Shah ,  Periannan Chidambaram

IPC: H03H9/05 ,  H01L25/04 ,  H03H9/02 ,  H03H9/145 ,  H03H9/64 ,  H10N30/02 ,  H10N30/87 ,  H10N30/88 ,  H03H3/02

CPC classification number: H03H9/058 ,  H01L25/04 ,  H03H3/02 ,  H03H9/02992 ,  H03H9/14544 ,  H03H9/64 ,  H10N30/02 ,  H10N30/875 ,  H10N30/883

Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

公开(公告)号：US11652064B2

公开(公告)日：2023-05-16

申请号：US16706167

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Je-Hsiung Lan ,  Ranadeep Dutta

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/552 ,  H01L24/08 ,  H01L24/80 ,  H01L25/16 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/3025

Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

公开(公告)号：US11437367B2

公开(公告)日：2022-09-06

申请号：US16854313

申请日：2020-04-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Ranadeep Dutta ,  Jonghae Kim

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H03F3/213

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

公开(公告)号：US11024728B2

公开(公告)日：2021-06-01

申请号：US16276762

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/205 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/06

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region and a collector region. The collector region may include a proton implant region having an edge aligned with an edge of the emitter region. In certain aspects, the HBT device also includes a base region disposed between the emitter region and the collector region.

公开(公告)号：US10340289B2

公开(公告)日：2019-07-02

申请号：US15581254

申请日：2017-04-28

Applicant: QUALCOMM INCORPORATED

Inventor： Ranadeep Dutta ,  Antonino Scuderi ,  Wing Sy

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H03F3/195 ,  H03F3/24 ,  H03F1/22

Abstract: An amplifier includes a cascode structure comprising a first transistor having first characteristics coupled to a second transistor having second characteristics different than the first characteristics, the first transistor formed with the second transistor on a single diffusion.

公开(公告)号：US20160126240A1

公开(公告)日：2016-05-05

申请号：US14991868

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L23/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823857 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7833 ,  H01L2924/0002 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2200/432 ,  H03F2203/7209 ,  H03F2203/7236 ,  H01L2924/00

Abstract: A device includes a first radio frequency (RF) component on a die. The first RF component includes a first lightly doped region having a first value of a characteristic, and the first RF component is configured to operate in a first RF band associated with a first frequency. The device further includes a second RF component on the die. The second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value. The second RF component is configured to operate in a second RF band associated with a second frequency that is different from the first frequency.

Abstract translation: 器件包括管芯上的第一射频（RF）部件。 第一RF分量包括具有特征的第一值的第一轻掺杂区域，并且第一RF分量被配置为在与第一频率相关联的第一RF频带中操作。 该器件还包括管芯上的第二RF部件。 第二RF分量包括具有不同于第一值的特性的第二值的第二轻掺杂区域。 第二RF分量被配置为在与第一频率不同的第二频率相关联的第二RF频带中操作。

公开(公告)号：US12283607B2

公开(公告)日：2025-04-22

申请号：US17349724

申请日：2021-06-16

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Je-Hsiung Lan ,  Ranadeep Dutta

IPC: H01F27/28 ,  H01F17/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/66 ,  H01L49/02 ,  H01P3/08 ,  H01P11/00

Abstract: A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

公开(公告)号：US20250047262A1

公开(公告)日：2025-02-06

申请号：US18363233

申请日：2023-08-01

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H03H9/25 ,  H03H3/08 ,  H03H9/145 ,  H03H9/64

Abstract: An acoustic device includes circuit elements, such as analog circuit components, between the first and second substrate and coupled to an acoustic resonator to form an acoustic filter within the acoustic device. In some examples, forming the circuit elements between the first substrate and the second substrate includes forming the first circuit elements in insulating material on the second substrate before coupling the second substrate to a first side of the first substrate. The circuit elements disposed between the first and second substrates may include capacitors, inductors, and electrical interconnects coupled to the acoustic resonator on the first substrate. Additional features may be included in the insulating material. The acoustic device avoids the need for bulky analog components coupled to the acoustic resonator via long interconnects through a package substrate, making it possible to reduce an acoustic device's package size.