公开(公告)号：US10333007B2

公开(公告)日：2019-06-25

申请号：US15686827

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Yun Yue ,  Chuan-Hsing Chen ,  Bin Yang ,  Lixin Ge ,  Ken Liao

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L23/482 ,  H01L23/485 ,  H01L23/66

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

公开(公告)号：US08980708B2

公开(公告)日：2015-03-17

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Bin Yang ,  P R Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L21/8244 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的至少一部分的第一电容器板和具有至少一部分MIM电容器层的第二电容器板。

公开(公告)号：US20190181137A1

公开(公告)日：2019-06-13

申请号：US15835810

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Lixin Ge

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/088 ,  H03K19/0185 ,  G06F17/50 ,  H01L21/762

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

公开(公告)号：US10247617B2

公开(公告)日：2019-04-02

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  G01K7/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L49/02 ,  G01K7/18 ,  H01L23/34 ,  H01L23/522 ,  H01L27/06

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US11296083B2

公开(公告)日：2022-04-05

申请号：US16811762

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Lixin Ge ,  Kwanyong Lim ,  Jun Chen

IPC: H01L27/092 ,  H01L23/522 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

公开(公告)号：US20190378904A1

公开(公告)日：2019-12-12

申请号：US16002459

申请日：2018-06-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Ye Lu ,  Lixin Ge

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

公开(公告)号：US09269492B2

公开(公告)日：2016-02-23

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Pr Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/38 ,  H01G4/005 ,  H01L49/02 ,  H01G4/33 ,  H01G4/10

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US20140231957A1

公开(公告)日：2014-08-21

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Bin Yang ,  PR Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L23/538 ,  H01L27/08

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上互连层的至少一部分的第一电容器板和具有MIM电容层的至少一部分的第二电容器板。

公开(公告)号：US20140092523A1

公开(公告)日：2014-04-03

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/005 ,  H01G4/38

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US20210280582A1

公开(公告)日：2021-09-09

申请号：US16811762

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Lixin Ge ,  Kwanyong Lim ,  Jun Chen

IPC: H01L27/092 ,  H01L23/522 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/06 ,  H01L29/10

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.