公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20210217699A1

公开(公告)日：2021-07-15

申请号：US16738127

申请日：2020-01-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail comprises a first conductive layer, a barrier layer, and a second conductive layer comprising copper. The barrier layer is disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20180197743A1

公开(公告)日：2018-07-12

申请号：US15910929

申请日：2018-03-02

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28123 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20190304919A1

公开(公告)日：2019-10-03

申请号：US15936964

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： John ZHU ,  Da YANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a metal contact comprising a first hybrid interconnect structure disposed within a metallization layer, and a metal comprising a second hybrid interconnect structure disposed within the metallization layer, wherein each of the first and the second hybrid interconnect structures has a top portion and a bottom portion, and wherein the top portion of each of the first and the second hybrid interconnect structures comprises a metal element that is suitable for chemical mechanical planarization (CMP) and the bottom portion of each of the first and the second hybrid interconnect structures comprises ruthenium (Ru). The metal element may comprise cobalt (Co).

公开(公告)号：US20160343661A1

公开(公告)日：2016-11-24

申请号：US15159744

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Stanley Seungchul SONG ,  Kern RIM ,  John Jianhong ZHU

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/45 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L27/0207

Abstract: A MOS device includes a first interconnect extending in a first direction, the first interconnect being configured in a metal layer. The MOS device further includes a second interconnect extending in the first direction parallel to the first interconnect, the second interconnect being configured in the metal layer. The MOS device further includes a gate interconnect extending in a second direction orthogonal to the first direction, the gate interconnect being situated in a first layer below the metal layer, wherein the gate interconnect is coupled to the first interconnect by a first via. The MOS device further includes a third interconnect extending in the second direction, the third interconnect being coupled to both the first and second interconnects, wherein the third interconnect is coupled to the first interconnect by a second via, and wherein the second via contacts the first via.

Abstract translation: MOS器件包括沿第一方向延伸的第一互连，第一互连配置在金属层中。 MOS器件还包括在第一方向上平行于第一互连延伸的第二互连，第二互连配置在金属层中。 MOS器件还包括在与第一方向正交的第二方向上延伸的栅极互连，栅极互连位于金属层下方的第一层中，其中栅极互连通过第一通孔耦合到第一互连。 MOS器件还包括在第二方向上延伸的第三互连，第三互连件耦合到第一和第二互连件，其中第三互连通过第二通孔耦合到第一互连，并且其中第二通孔接触第一互连 通过。

公开(公告)号：US20150325515A1

公开(公告)日：2015-11-12

申请号：US14274470

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

公开(公告)号：US20210118883A1

公开(公告)日：2021-04-22

申请号：US16654774

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Stanley Seungchul SONG ,  Jun YUAN ,  Kern RIM

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

公开(公告)号：US20180122824A1

公开(公告)日：2018-05-03

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20180082906A1

公开(公告)日：2018-03-22

申请号：US15271043

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley SONG ,  Jeffrey XU ,  Da YANG ,  Kern RIM ,  Choh fei YEAP

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/3065

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

公开(公告)号：US20160071847A1

公开(公告)日：2016-03-10

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  Matthew Michael NOWAK ,  Choh Fei YEAP ,  Roawen CHEN

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。