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    DRAM SUB-ARRAY LEVEL REFRESH
    4.
    发明申请
    DRAM SUB-ARRAY LEVEL REFRESH 有权

    公开(公告)号：US20150009769A1

    公开(公告)日：2015-01-08

    申请号：US14088098

    申请日：2013-11-22

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu DONG ,  Jungwon SUH

    IPC: G11C11/406

    CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611

    Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

    Abstract translation: 耦合到具有多个存储器单元的子阵列的存储器芯片的存储器控​​制器被配置为确定存储器芯片的配置。 存储器控制器被配置为读取存储器芯片的子阵列配置并且检测外部命令和刷新操作之间的子阵列电平冲突。 内存控制器在刷新操作期间保持一个或多个非冲突的页面打开。

    METHOD AND APPARATUS FOR USING A DEFECTIVE DYNAMIC READ-ONLY MEMORY REGION
    5.
    发明申请
    METHOD AND APPARATUS FOR USING A DEFECTIVE DYNAMIC READ-ONLY MEMORY REGION 审中-公开
    使用有缺陷的动态只读存储器区域的方法和装置

    公开(公告)号：US20150331623A1

    公开(公告)日：2015-11-19

    申请号：US14280006

    申请日：2014-05-16

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu DONG

    IPC: G06F3/06 ,  G06F11/07

    CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0787

    Abstract: Methods and apparatus for using a defective dynamic read-only memory region are provided. In an example, a defective Dynamic Random Access Memory (DRAM) page is used, instead of being disabled. A compress-and-store technique uses a non-defective region of a defective DRAM page to store page-swapping data. This allows the defective DRAM page to be used as a fast swapping resource, which results in increasing system performance, saving materials, saving time, and saving energy. In an example, a method for using a defective DRAM page in a DRAM includes using an error history table to determine that the defective DRAM page has a defective block, and updating a defect table with an address of the defective block. The defect table is used to determine an address of a good block in the defective DRAM page. Page swap data is compressed and stored in the good block in the defective DRAM page.

    Abstract translation: 提供了使用有缺陷的动态只读存储器区域的方法和装置。 在一个示例中，使用有缺陷的动态随机存取存储器（DRAM）页面，而不是被禁用。 压缩和存储技术使用有缺陷的DRAM页面的无缺陷区域来存储页面交换数据。 这样就可以将有缺陷的DRAM页面用作快速交换资源，从而提高系统性能，节省材料，节省时间并节省能源。 在一个示例中，用于在DRAM中使用缺陷DRAM页面的方法包括使用错误历史表来确定有缺陷的DRAM页面具有缺陷块，以及用缺陷块的地址更新缺陷表。 缺陷表用于确定有缺陷的DRAM页面中的良好块的地址。 页面交换数据被压缩并存储在有缺陷的DRAM页面的好块中。

    SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY
    6.
    发明申请
    SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY 审中-公开
    并联读/写磁阻存储器的系统和方法

    公开(公告)号：US20150310904A1

    公开(公告)日：2015-10-29

    申请号：US14263632

    申请日：2014-04-28

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Xiangyu DONG

    IPC: G11C11/16

    CPC classification number: G11C11/1653 ,  G11C7/1039 ,  G11C7/1042 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

    Abstract: In a memory having a first memory cell array, a second memory cell array, an address is received on an address port. Based on the address, an internal address is transmitted, and it is latched and held for a first interval as a first array address. The first memory cell array is accessed over the first interval, based on the first array address. Another address is received at the address port, during the first interval, and another internal address is transmitted, and latched and held for a second interval that overlaps the first interval, as a second array address. The second memory cell array is accessed during the second interval, based on the second array address.

    Abstract translation: 在具有第一存储单元阵列的存储器中，第二存储单元阵列在地址端口上接收地址。 基于该地址，发送内部地址，并将其锁存并保持第一间隔作为第一阵列地址。 基于第一个阵列地址，第一个存储单元阵列在第一个时间间隔内被访问。 在第一间隔期间在地址端口处接收另一地址，并且发送另一内部地址，并将其锁存并保持与第一间隔重叠的第二间隔作为第二阵列地址。 基于第二阵列地址在第二间隔期间访问第二存储单元阵列。

    REFRESH SCHEME FOR MEMORY CELLS WITH NEXT BIT TABLE
    8.
    发明申请
    REFRESH SCHEME FOR MEMORY CELLS WITH NEXT BIT TABLE 有权
    具有下一个位表的记忆细胞的刷新方案

    公开(公告)号：US20150162065A1

    公开(公告)日：2015-06-11

    申请号：US14276452

    申请日：2014-05-13

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill KIM ,  Jungwon SUH ,  Xiangyu DONG

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G06F12/0207 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

    Abstract translation: 存储器刷新控制技术允许基于外部1×刷新率的灵活的内部刷新率，并允许基于外部1×刷新率跳过强存储器行的刷新周期。 存储器控制器通过从刷新地址计数器读取刷新地址，从弱地址表读取弱地址并且至少部分地基于与弱地址组合的下一个比特序列产生下一个弱地址值来执行存储器刷新。 存储器控制器将刷新地址与弱地址和下一个弱地址值进行比较。 基于比较，存储器控制器在跳过刷新周期，刷新刷新地址，刷新弱地址以及刷新刷新地址和弱地址之间进行选择。

    INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES
    10.
    发明申请
    INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES 有权
    插入式重写计数器支持多种内存刷新率

    公开(公告)号：US20150016204A1

    公开(公告)日：2015-01-15

    申请号：US14149543

    申请日：2014-01-07

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu DONG ,  Jung Pill KIM

    IPC: G11C11/406

    CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    Abstract: A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations.

    Abstract translation: 存储器刷新方法包括确定在存储器块的正常行的规则调度的刷新操作中插入存储器块的弱行的刷新操作的位置。 刷新操作以基本恒定的刷新率发生。 要插入的位置基于实际的弱页面地址。 该方法还包括在所确定的位置处执行插入的刷新操作，以协调在规则排列的刷新操作之间插入的刷新操作的分布。

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