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    ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERROR RATE (WER) TO IMPROVE WER YIELD, AND RELATED METHODS AND SYSTEMS
    1.
    发明申请
    ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERROR RATE (WER) TO IMPROVE WER YIELD, AND RELATED METHODS AND SYSTEMS 有权
    基于写错误率（WER）来调整电阻记忆写驱动强度，以提高功能，以及相关方法和系统

    公开(公告)号：US20160276009A1

    公开(公告)日：2016-09-22

    申请号：US14818809

    申请日：2015-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

    IPC: G11C11/16 ,  G11C29/44

    CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

    Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

    Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

    BIT RECOVERY SYSTEM
    5.
    发明申请
    BIT RECOVERY SYSTEM 有权
    位恢复系统

    公开(公告)号：US20150149864A1

    公开(公告)日：2015-05-28

    申请号：US14088867

    申请日：2013-11-25

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G06F11/10

    CPC classification number: G06F11/102 ,  G06F11/1064 ,  G06F12/00

    Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

    Abstract translation: 特定设备包括基于电阻的存储器件，标签随机存取存储器（RAM）和位恢复（BR）存储器。 基于电阻的存储器件被配置为存储与数据值相关联的数据值和纠错码（ECC）数据。 标签RAM被配置为存储将主存储器的存储器地址映射到高速缓冲存储器的字线的信息，其中高速缓冲存储器包括基于电阻的存储器件。 BR存储器被配置为存储与数据值相关联的附加纠错数据，其中BR存储器对应于易失性存储器设备。

    ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS
    6.
    发明申请
    ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS 有权
    一次性可编程元件的错误检测和校正

    公开(公告)号：US20140215294A1

    公开(公告)日：2014-07-31

    申请号：US13752419

    申请日：2013-01-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

    IPC: G06F11/08

    CPC classification number: G06F11/1048 ,  G11C11/16 ,  G11C17/02 ,  G11C17/146 ,  G11C17/18 ,  G11C29/027 ,  G11C2029/4402

    Abstract: A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.

    Abstract translation: 电路包括第一个一次性可编程（OTP）元件和第二个OTP元件。 电路还包括耦合以从第一OTP元件接收数据的第一表示的错误检测电路。 电路还包括响应于错误检测电路的输出的输出电路，以基于数据的第一表示或基于来自第二OTP元件的数据的第二表示来输出OTP读取结果。

    MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION
    7.
    发明申请
    MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION 有权
    存储单元存储配置信息的存储单元

    公开(公告)号：US20140140162A1

    公开(公告)日：2014-05-22

    申请号：US13680361

    申请日：2012-11-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

    IPC: G11C8/16

    CPC classification number: G11C7/20 ,  G11C16/20 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

    Abstract: A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device.

    Abstract translation: 提供了包括单元阵列和易失性存储装置的存储装置。 单元阵列可以包括多个字线，多个位线，其中字线和位线的选择定义存储器单元地址，以及用于存储单元阵列的配置信息的非易失性保留字线。 易失性存储设备耦合到单元阵列。 来自非易失性保留字线的配置信息在上电或初始化存储器件时被复制到易失性存储设备。

    RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE
    8.
    发明申请
    RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE 有权
    具有两个二极管访问器件的基于电阻的存储器

    公开(公告)号：US20140119097A1

    公开(公告)日：2014-05-01

    申请号：US14147817

    申请日：2014-01-06

    Applicant: QUALCOMM Incorporated

    Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

    Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

    Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

    Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems
    10.
    发明授权
    Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems 有权

    公开(公告)号：US09753874B2

    公开(公告)日：2017-09-05

    申请号：US14627318

    申请日：2015-02-20

    Applicant: QUALCOMM Incorporated

    Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

    IPC: G06F13/28 ,  G06F12/02 ,  G06F9/44

    CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

    Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

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