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    Flexible Dual Ranks Memory System To Boost Performance
    1.
    发明公开
    Flexible Dual Ranks Memory System To Boost Performance 审中-公开

    公开(公告)号：US20240078202A1

    公开(公告)日：2024-03-07

    申请号：US17929946

    申请日：2022-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Pankaj DESHMUKH ,  Shyamkumar THOZIYOOR ,  Subbarao PALACHARLA

    IPC: G06F13/16 ,  G06F12/06

    CPC classification number: G06F13/1694 ,  G06F12/0623

    Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

    MEMORY WITH DYNAMIC VOLTAGE SCALING
    2.
    发明申请
    MEMORY WITH DYNAMIC VOLTAGE SCALING 有权

    公开(公告)号：US20210065772A1

    公开(公告)日：2021-03-04

    申请号：US16945303

    申请日：2020-07-31

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

    IPC: G11C11/4074 ,  G11C11/409

    Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
    3.
    发明申请
    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20190056990A1

    公开(公告)日：2019-02-21

    申请号：US15682533

    申请日：2017-08-21

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G06F11/10

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    DATA BANDWIDTH SCALABLE MEMORY SYSTEM
    5.
    发明申请
    DATA BANDWIDTH SCALABLE MEMORY SYSTEM 审中-公开
    数据带宽可调存储系统

    公开(公告)号：US20160291634A1

    公开(公告)日：2016-10-06

    申请号：US14677752

    申请日：2015-04-02

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  David Ian WEST ,  Dexter Tamio CHUN

    IPC: G06F1/14

    CPC classification number: G06F1/3253 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A clock is distributed to a processor-side base mode clocked transceiver and to a memory-side base mode clocked transceiver, interfacing respective ends of a data lane between a processor and the memory, for duplex communicating over the data lane. Concurrent with the duplex communicating, a bandwidth mode switches between a base bandwidth mode and a scale-up mode. The scale-up mode enables scale-up clock lines that distribute the clock to a processor-side scale-up transceiver and to a memory-side scale-up transceiver, interfacing respective ends of a scale-up data lane between the processor and the memory, for additional duplex communicating over the scale-up data lane. The base bandwidth mode disables the scale-up clock lines, which disables communicating over the scale-up data lane.

    Abstract translation: 时钟被分配到处理器侧基本模式时钟收发器和存储器侧基本模式时钟收发器，将处理器和存储器之间的数据通道的相应端接口连接，以在数据通道上进行双向通信。 与双工通信同时，带宽模式在基带宽模式和放大模式之间切换。 放大模式可实现将时钟分配给处理器侧放大收发器和存储器侧放大收发器的放大时钟线，将处理器与处理器之间的放大数据通道的各个端点相连接 存储器，用于通过放大数据通道进行额外的双工通信。 基带宽模式禁用放大时钟线，禁止通过放大数据通道进行通信。

    DRAM SUB-ARRAY LEVEL REFRESH
    6.
    发明申请
    DRAM SUB-ARRAY LEVEL REFRESH 有权

    公开(公告)号：US20150009769A1

    公开(公告)日：2015-01-08

    申请号：US14088098

    申请日：2013-11-22

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu DONG ,  Jungwon SUH

    IPC: G11C11/406

    CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611

    Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

    Abstract translation: 耦合到具有多个存储器单元的子阵列的存储器芯片的存储器控​​制器被配置为确定存储器芯片的配置。 存储器控制器被配置为读取存储器芯片的子阵列配置并且检测外部命令和刷新操作之间的子阵列电平冲突。 内存控制器在刷新操作期间保持一个或多个非冲突的页面打开。

    Low Power Memory System Using Dual Input-Output Voltage Supplies
    7.
    发明公开
    Low Power Memory System Using Dual Input-Output Voltage Supplies 审中-公开

    公开(公告)号：US20230154502A1

    公开(公告)日：2023-05-18

    申请号：US18150155

    申请日：2023-01-04

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Joon Young PARK ,  Mahalingam NAGARAJAN

    IPC: G11C5/14 ,  H03K7/02

    CPC classification number: G11C5/147 ,  H03K7/02

    Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

    METHOD AND APPARATUS FOR MULTIPLE-BIT DRAM ERROR RECOVERY
    10.
    发明申请
    METHOD AND APPARATUS FOR MULTIPLE-BIT DRAM ERROR RECOVERY 有权
    用于多位DRAM错误恢复的方法和装置

    公开(公告)号：US20150143198A1

    公开(公告)日：2015-05-21

    申请号：US14081645

    申请日：2013-11-15

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter CHUN ,  Jung Pill KIM ,  Hyunsuk SHIN ,  Jungwon SUH

    IPC: G06F11/10 ,  G11C29/00

    CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G06F11/14 ,  G11C29/765

    Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

    Abstract translation: 当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。 在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且配置重新映射器，以便将来对页面的访问被重定向到 冗余页面。

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